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Poster in an International Conference

Gatewaying IEEE 1149.1 and IEEE 1149.7 test access ports

José Martins Ferreira (Author) (FEUP); Francisco R. Fernandes (Author) (Other); Ricardo J. S. Machado (Author) (Other); Manuel G. Gericota (Author) (Other)

2012

Scientific classification Indexing Documents

File name	Description	Size
20.P-IOLTS_2012		248.93 KB

Chapter or Part of a Book

Run-time Defragmentation for Dynamically Reconfigurable Hardware

Manuel G. Gericota (Author) (Other); Gustavo R. Alves (Author) (Other); Miguel L. Silva (Author) (Other); José M. Ferreira (Author) (FEUP)

2005

Scientific classification

Article in International Scientific Journal

Reliability and availability in reconfigurable computing: A basis for a common solution

Manuel G. Gericota (Author) (Other); Gustavo R. Alves (Author) (Other); Miguel L. Silva (Author) (Other); José M. Ferreira (Author) (FEUP)

2008

Scientific classification Indexing Documents

File name	Description	Size
5.J-ToVLSIS_2008_59326	Reliability and Availability in Reconfigurable Computing: A Basis for a Common Solution	1446.79 KB

Real-time fault injection using enhanced on-chip debug infrastructures

José Martins Ferreira (Author) (FEUP); André V. Fidalgo (Author) (Other); Manuel G. Gericota (Author) (Other); Gustavo R. Alves (Author) (Other)

2011

Scientific classification Indexing Documents

File name	Description	Size
8.J-MM_2011		587.98 KB

Article in International Conference Proceedings Book

Techniques to improve the reliability of fault-tolerant systems based on self-reconfigurable FPGAs

José Martins Ferreira (Author) (FEUP); André Roberto Guerra (Author) (Other); Manuel G. Gericota (Author) (Other)

2005

Scientific classification Documents

File name	Description	Size
67.C-REC_2005		239.89 KB

Restoring Reliability in Fault Tolerant Reconfigurable Systems

José Martins Ferreira (Author) (FEUP); Manuel G. Gericota (Author) (Other)

2005

Scientific classification Documents

File name	Description	Size
68.C-REC_2005		164.48 KB

FPGA architectures for reconfigurable computing

José M. Ferreira (Author) (FEUP); Manuel G. Gericota (Author) (Other); Gustavo R. Alves (Author) (Other)

2007

Scientific classification Documents

File name	Description	Size
87.C-REC_2007		218.60 KB

Assessing Defragmentation Strategies for FPGAs

Manuel G. Gericota (Author) (Other); Gustavo R. Alves (Author) (Other); Luís F. Lemos (Author) (Other); José M. Ferreira (Author) (FEUP)

2006

Scientific classification Documents

File name	Description	Size
73.C-REC_2006_64172	Assessing Defragmentation Strategies for FPGAs	392.99 KB

Article in International Conference Proceedings Book

The RaT technique for concurrent test of dinamically reconfigurable hardware

Manuel G. Gericota (Author) (Other); Gustavo R. Alves (Author) (Other); José M. Ferreira (Author) (FEUP)

2000

Scientific classification Documents

File name	Description	Size
45.C-DCIS_2000_65723	The RaT technique for concurrent test of dinamically reconfigurable hardware	209.96 KB

Run-time management of logic resources on reconfigurable systems

Manuel G. Gericota (Author) (Other); Gustavo R. Alves (Author) (Other); Miguel L. Silva (Author) (Other); José M. Ferreira (Author) (FEUP)

2003

Scientific classification Indexing Documents

File name	Description	Size
60.C-DATE_2003_58728	Run-Time Management of Logic Resources on Reconfigurable Systems	364.54 KB

Programmable logic devices: a test approach for the Input / Output blocks and Pad-to-Pin interconnections

Manuel G. Gericota (Author) (Other); Gustavo R. Alves (Author) (Other); Miguel L. Silva (Author) (Other); José M. Ferreira (Author) (FEUP)

2003

Scientific classification Documents

File name	Description	Size
59.C-LATW_2003_58727	Programmable Logic Devices: A Test Approach for the Input / Output Blocks and Pad-to-Pin Interconnections	354.19 KB

On-line self-healing of circuits implemented on reconfigurable FPGAs

Manuel G. Gericota (Author) (Other); Luís F. Lemos (Author) (Other); Gustavo R. Alves (Author) (Other); José M. Ferreira (Author) (FEUP)

2007

Scientific classification Documents

File name	Description	Size
94.C-IOLTS_2007_59322	On-Line Self-Healing of Circuits Implemented on Reconfigurable FPGAs	319.39 KB

On-line defragmentation for run-time partially reconfigurable FPGAs

Manuel G. Gericota (Author) (Other); Gustavo R. Alves (Author) (Other); Miguel L. Silva (Adapter) (FEUP); José M. Ferreira (Author) (FEUP)

2002

Scientific classification Indexing Documents

File name	Description	Size
56.C-FPL_2002_65736	On-line defragmentation for run-time partially reconfigurable FPGAs	1099.07 KB

Improved dependability for dynamically reconfigurable hardware: restoration of the reliability index via replication and error correction

José Martins Ferreira (Author) (FEUP); Manuel G. Gericota (Author) (Other)

2004

Scientific classification Documents

File name	Description	Size
65.C-DAK-forum_2004_Slides		789.83 KB

HDL approach to board-level BIST

Gustavo R. Alves (Author) (Other); Manuel G. Gericota (Author) (Other); José L. Ramalho (Author) (Other); José M. M. Ferreira (Author) (FEUP)

1993

Scientific classification Indexing Documents

File name	Description	Size
6.C-EURO-DAC_1993_52337	An HDL Approach to Board-Level BIST	369.68 KB

Dynamic replication : the core of a truly non-intrusive SRAM-based FPGA structural concurrent test methodology

Manuel G. Gericota (Author) (Other); Gustavo R. Alves (Author) (Other); Miguel L. Silva (Author) (FEUP); José M. Ferreira (Author) (FEUP)

2002

Scientific classification Documents

File name	Description	Size
51.C-LATW_2002_67581	Dynamic replication : the core of a truly non-intrusive SRAM-based FPGA structural concurrent test methodology	198.72 KB

DRAFT: A scanning test methodology for dynamic and partially reconfigurable FPGAs

Manuel G. Gericota (Author) (Other); Gustavo R. Alves (Author) (Other); Miguel L. Silva (Author) (Other); José M. Ferreira (Author) (FEUP)

2001

Scientific classification Documents

File name	Description	Size
47.C-ETW_2001_65724	DRAFT: A Scanning Test Methodology for Dynamic and Partially Reconfigurable FPGAs	157.80 KB

Concurrent replication of active logic blocks: a core solution for online testing and logic space defragmentation in reconfigurable systems

Manuel G. Gericota (Author) (Other); Gustavo R. Alves (Author) (Other); Miguel L. Silva (Author) (Other); J. M. Martins Ferreira (Author) (FEUP)

2003

Scientific classification Documents

File name	Description	Size
61.C-DAK-forum_2003_Text_67049	Concurrent replication of active logic blocks: a core solution for online testing and logic space defragmentation in reconfigurable systems	261.87 KB

BIST for 1149.1-compatible boards: a low-cost and maximum-flexibility solution(

José M. M. Ferreira (Author) (FEUP); Manuel G. Gericota (Author) (Other); José L. Ramalho (Author) (Other); Gustavo R. Alves (Author) (Other)

1993

Scientific classification Indexing Documents

File name	Description	Size
8.C-ITC_1993_54871	BIST for 1149.1-Compatible Boards: A Low-Cost and Maximum-Flexibility Solution	981.99 KB

Active replication : towards a truly SRAM-based FPGA on-line concurrent testing

Manuel G. Gericota (Author) (Other); Gustavo R. Alves (Author) (Other); Miguel L. Silva (Author) (FEUP); José M. Ferreira (Author) (FEUP)

2002

Scientific classification Indexing Documents

File name	Description	Size
54.C-IOLTW_2002_67375	Active replication : towards a truly SRAM-based FPGA on-line concurrent testing	214.32 KB

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