FPGA architectures for reconfigurable computing

• Type: Article in International Conference Proceedings Book
• Date: 2007-02

Authors

José M. Ferreira (Author) FEUP; Manuel G. Gericota (Author) Other; Gustavo R. Alves (Author) Other

Conference proceedings National

Title: Actas das III Jornadas sobre Sistemas Reconfiguráveis

Pages: 22-25

III Jornadas sobre Sistemas Reconfiguráveis (REC'07)

Lisbon, 8 a 9 de Fevereiro de 2007

Scientific classification

CORDIS: Technological sciences > Engineering > Electrical engineering

FOS: Engineering and technology > Electrical engineering, Electronic engineering, Information engineering

Other information

Abstract (EN): To accelerate the execution of an application, repetitive logic and arithmetic computation tasks may be mapped to reconfigurable hardware, since dedicated hardware can deliver much higher speeds than those of a general-purpose processor. However, this is only feasible if the run-time reconfiguration of new tasks is fast enough, so as not to delay application execution. Currently, this is opposed by architectural constraints intrinsic to current Field-Programmable Logic Array (FPGA) architectures. Despite all new features exhibited by current FPGAs, architecturally they are still largely based on general-purpose architectures that are inadequate for the demands of reconfigurable computing. Large configuration file sizes and poor hardware and software support for partial and dynamic reconfiguration limits the acceleration that reconfigurable computing may bring to applications. The objective of this work is the identification of the architectural limitations exhibited by current FPGAs that prevent reconfigurable computing systems to achieve a high efficiency and performance and the proposal of alternatives to its resolution.

Language: English

Type (Professor's evaluation): Scientific

No. of pages: 4