Programmable logic devices: a test approach for the Input / Output blocks and Pad-to-Pin interconnections

• Type: Article in International Conference Proceedings Book
• Date: 2003

Authors

Manuel G. Gericota (Author) Other; Gustavo R. Alves (Author) Other; Miguel L. Silva (Author) Other; José M. Ferreira (Author) FEUP

Conference proceedings International

Title: Proceedings of the 4th IEEE Latin American Test Workshop (LATW 03)

Pages: 72-77

4th IEEE Latin American Test Workshop (LATW 03)

Natal (Brasil), 16 a 19 de Fevereiro de 2003

Scientific classification

FOS: Engineering and technology > Electrical engineering, Electronic engineering, Information engineering

Other information

Abstract (EN): Dynamically reconfigurable systems based on partial and dynamically reconfigurable FPGAs may have their functionality partially modified at run-time without stopping the operation of the whole system. The efficient management of the logic space available is one of the biggest problems faced by these systems. When the sequence of reconfigurations to be performed is not predictable, resource allocation decisions have to be made on-line. A rearrangement may be necessary to get enough contiguous space to implement incoming functions, avoiding the spreading of their components and the resulting degradation of system performance. A new software tool that helps to handle the problems posed by the consecutive reconfiguration of the same logic space is presented in this paper. This tool uses a novel on-line rearrangement procedure to solve fragmentation problems and to rearrange the logic space in a way completely transparent to the applications currently running.

Language: English

Type (Professor's evaluation): Scientific

No. of pages: 6