HDL approach to board-level BIST

• Type: Article in International Conference Proceedings Book
• Date: 1993

Authors

Gustavo R. Alves (Author) Other; Manuel G. Gericota (Author) Other; José L. Ramalho (Author) Other; José M. M. Ferreira (Author) FEUP

Conference proceedings International

Title: Proceedings of the European Design Automation Conference

Pages: 410-415

Euro-DAC - European Design Automation Conference

Hamburgo, Alemanha, 20 - SETEMBRO - 1993

Indexing

ISI Web of Science

Scopus

INSPEC

Scientific classification

CORDIS: Technological sciences > Engineering > Electrical engineering

FOS: Engineering and technology > Electrical engineering, Electronic engineering, Information engineering

Other information

DOI: 10.1109/EURDAC.1993.410669

Abstract (EN): Boundary scan is now the most promising technology for testing high-complexity printed circuit boards. The number of BST components available to board-level designers is however still restricted, limiting the achievable fault coverage. The requirements to improve board-level testability are analyzed, and a corresponding set of testability building blocks are proposed. A high flexibility and reduced cost solution is described, which implements these blocks on medium-complexity PLDs using a simple and powerful HDL.

Language: English

Type (Professor's evaluation): Scientific

No. of pages: 6