DRAFT: A scanning test methodology for dynamic and partially reconfigurable FPGAs

• Type: Article in International Conference Proceedings Book
• Date: 2001

Authors

Manuel G. Gericota (Author) Other; Gustavo R. Alves (Author) Other; Miguel L. Silva (Author) Other; José M. Ferreira (Author) FEUP

Conference proceedings International

Title: Proceedings of the European Test Workshop ETW'01

Pages: 113-115

European Test Workshop ETW¿01

Estocolmo, Suécia, 29 de Maio a 1 de Junho de 2001

Scientific classification

CORDIS: Technological sciences > Engineering > Electrical engineering

FOS: Engineering and technology > Electrical engineering, Electronic engineering, Information engineering

Other information

Abstract (EN): A new class of FPGAs that enable partial and dynamic reconfiguration without disturbing system operation, raised a new test challenge: how to assure a continuously fault-free operation, independently of the circuit present after many reconfiguration processes. A new on-line test method for those FPGAs is proposed, based on a scanning methodology and in the reuse of the IEEE 1149.1 Boundary Scan test infrastructure, already widely employed for In-System Programming.

Language: English

Type (Professor's evaluation): Scientific

No. of pages: 3