The RaT technique for concurrent test of dinamically reconfigurable hardware

• Type: Article in International Conference Proceedings Book
• Date: 2000

Authors

Manuel G. Gericota (Author) Other; Gustavo R. Alves (Author) Other; José M. Ferreira (Author) FEUP

Conference proceedings International

Title: Proceedings of DCIS'00 - XV Design of Circuits and Integrated Systems Conference

Pages: 337-340

XV Design of Circuits and Integrated Systems Conference DCIS'00

Montpellier, França, 21 a 24 de Novembro de 2000

Scientific classification

FOS: Engineering and technology > Electrical engineering, Electronic engineering, Information engineering

CORDIS: Technological sciences > Engineering > Electrical engineering

Other information

Abstract (EN): A new class of FPGAs that enable partial and dynamic reconfiguration has been recently introduced into the market, opening exciting possibilities for dynamically reconfigurable hardware systems. While enabling concurrent reconfiguration without disturbing system operation, this technology also raises a new test challenge: the reconfiguration process can activate faults which would otherwise not be visible. This paper proposes a structural concurrent test method that reuses the IEEE 1149.1 infrastructure, exploiting the same dynamic and partially reconfigurable features underlying this test challenge.

Language: English

Type (Professor's evaluation): Scientific

No. of pages: 4