The RaT technique for concurrent test of dinamically reconfigurable hardware

• Tipo: Artigo em Livro de Atas de Conferência Internacional
• Data: 2000

Autores

Manuel G. Gericota (Autor) Outra; Gustavo R. Alves (Autor) Outra; José M. Ferreira (Autor) FEUP

Ata de Conferência Internacional

Título: Proceedings of DCIS'00 - XV Design of Circuits and Integrated Systems Conference

Páginas: 337-340

XV Design of Circuits and Integrated Systems Conference DCIS'00

Montpellier, França, 21 a 24 de Novembro de 2000

Classificação Científica

FOS: Ciências da engenharia e tecnologias > Engenharia electrotécnica, electrónica e informática

CORDIS: Ciências Tecnológicas > Engenharia > Engenharia electrotécnica

Outras Informações

Abstract (EN): A new class of FPGAs that enable partial and dynamic reconfiguration has been recently introduced into the market, opening exciting possibilities for dynamically reconfigurable hardware systems. While enabling concurrent reconfiguration without disturbing system operation, this technology also raises a new test challenge: the reconfiguration process can activate faults which would otherwise not be visible. This paper proposes a structural concurrent test method that reuses the IEEE 1149.1 infrastructure, exploiting the same dynamic and partially reconfigurable features underlying this test challenge.

Idioma: Inglês

Tipo (Avaliação Docente): Científica

Nº de páginas: 4