Real-time fault injection using enhanced on-chip debug infrastructures

• Type: Article in International Scientific Journal
• Date: 2011-06

Authors

José Martins Ferreira (Author) FEUP; André V. Fidalgo (Author) Other; Manuel G. Gericota (Author) Other; Gustavo R. Alves (Author) Other

Journal

Title: Microprocessors and Microsystems

Vol. 35

Pages: 441-452

ISSN: 0141-9331

Publisher: Elsevier

Indexing

ISI Web of Science

Scopus

INSPEC

Scientific classification

CORDIS: Technological sciences > Engineering > Electrical engineering

FOS: Engineering and technology > Electrical engineering, Electronic engineering, Information engineering

Other information

DOI: 10.1016/j.micpro.2010.10.002

Abstract (EN): The rapid increase in the use of microprocessor-based systems in critical areas, where failures imply risks to human lives, to the environment or to expensive equipment, significantly increased the need for dependable systems, able to detect, tolerate and eventually correct faults. The verification and validation of such systems is frequently performed via fault injection, using various forms and techniques. However, as electronic devices get smaller and more complex, controllability and observability issues, and sometimes real time constraints, make it harder to apply most conventional fault injection techniques. This paper proposes a fault injection environment and a scalable methodology to assist the execution of real-time fault injection campaigns, providing enhanced performance and capabilities. Our proposed solutions are based on the use of common and customized on-chip debug (OCD) mechanisms, present in many modern electronic devices, with the main objective of enabling the insertion of faults in microprocessor memory elements with minimum delay and intrusiveness. Different configurations were implemented starting from basic Components Off-The-Shelf (COTS) microprocessors, equipped with real-time OCD infrastructures, to improved solutions based on modified interfaces, and dedicated OCD circuitry that enhance fault injection capabilities and performance. All methodologies and configurations were evaluated and compared concerning performance gain and silicon overhead

Language: English

Type (Professor's evaluation): Scientific

No. of pages: 12