Resumo (PT):
Abstract (EN):
A set of board-level testability blocks is proposed in this paper, with the aim of improving the fault coverage achievable on boards restricted to commercially available BST components. It is shown that a high flexibility and low-cost solution to board-level BIST is possible by combining an HDL-based implementation with the wide availability of medium-complexity PLDs.
Language:
English
Type (Professor's evaluation):
Scientific
No. of pages:
8
License type: