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Dynamic replication : the core of a truly non-intrusive SRAM-based FPGA structural concurrent test methodology

Title
Dynamic replication : the core of a truly non-intrusive SRAM-based FPGA structural concurrent test methodology
Type
Article in International Conference Proceedings Book
Year
2002
Authors
Manuel G. Gericota
(Author)
Other
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Gustavo R. Alves
(Author)
Other
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Miguel L. Silva
(Author)
FEUP
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José M. Ferreira
(Author)
FEUP
Conference proceedings International
Pages: 70-75
3rd IEEE Latin American Test Workshop (LATW'02)
Montevideo, Uruguai, 10 a 13 de Fevereiro de 2002
Scientific classification
FOS: Engineering and technology > Electrical engineering, Electronic engineering, Information engineering
CORDIS: Technological sciences > Engineering > Electrical engineering
Other information
Abstract (EN): The increasing use of reconfigurable computing platforms, employing SRAM-based FPGAs, opens exciting new possibilities since they enable the reutilization of same hardware resources to implement speed-critical computational tasks, without interrupting system operation. Nevertheless, larger dies and the use of smaller submicron scales in the manufacturing of this new kind of FPGAs increase the probability of lifetime operation failures, requiring new test / fault tolerance methods capable of assuring the reliability of the system. Structural concurrent test procedures become particularly important in this context, since it is now possible to replicate and release for test internal FPGA resources, concurrently with ¿ but not affecting ¿ system operation. A new dynamic replication process of active Configurable Logic Blocks (CLBs) is presented in this paper, which enables the implementation of a truly non-intrusive structural component test approach. The experimental results presented prove the effectiveness of this solution.
Language: English
Type (Professor's evaluation): Scientific
No. of pages: 6
License type: Click to view license CC BY-NC
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51.C-LATW_2002_67581 Dynamic replication : the core of a truly non-intrusive SRAM-based FPGA structural concurrent test methodology 198.72 KB
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