Publications with the same authors as the A boundary scan based one channel timing analyser publication

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Article in International Conference Proceedings Book

From Design-for-Test to Design-for-Debug-and-Test: Analysis of Requirements and Limitations for 1149.1

Gustavo Costa Alves (Author) (Other); José Martins Ferreira (Author) (FEUP)

1999

Scientific classification

From circuit simulation to circuit verification: an internal+boundary-scan-based solution

Gustavo Costa Alves (Author) (Other); Marcelo Lubaszewski (Author) (Other); Margrit Krug (Author) (Other); José Martins Ferreira (Author) (FEUP)

2000

Scientific classification Documents

File name	Description	Size
9.P-ETW_2000_53307	From Circuit Simulation to Circuit Verification: An Internal + Boundary- Scan-Based Solution	270.12 KB

Experimenting the 1149.1 and 1149.4 test infrastructures in a Web-accessible remote Lab (without Plug-ins!)

Gustavo Costa Alves (Author) (Other); Ricardo Costa (Author) (Other); André Fidalgo (Author) (Other); José Martins Ferreira (Author) (FEUP)

2001

Scientific classification

Dynamically rotate and free for test: the aath for FPGA concurrent test

Manuel Gericota (Author) (Other); Gustavo Costa Alves (Author) (Other); José Martins Ferreira (Author) (FEUP)

2001

Scientific classification Documents

File name	Description	Size
46.C-LATW_2001_52088	Dynamically Rotate And Free for Test: The Path for FPGA Concurrent Test	442.14 KB

DRAFT: An On-line Fault Detection Method for Dynamic and Partially Reconfigurable FPGAs

Manuel Gericota (Author) (Other); Gustavo Costa Alves (Author) (Other); Miguel L. Silva (Author) (Other); José Martins Ferreira (Author) (FEUP)

2001

Scientific classification Indexing Documents

File name	Description	Size
48.C-IOLTW_2001_53087	DRAFT: An On-line Fault Detection Method for Dynamic and Partially Reconfigurable FPGAs	154.43 KB

DRAFT: An On-line Concurrent Test for Partial and Dynamically Reconfigurable FPGAs

Manuel Gericota (Author) (Other); Gustavo Costa Alves (Author) (Other); Miguel L. Silva (Author) (Other); José Martins Ferreira (Author) (FEUP)

2001

Scientific classification Documents

File name	Description	Size
50.C-DCIS_2001_69352	DRAFT: An On-line Concurrent Test for Partial and Dynamically Reconfigurable FPGAs	169.21 KB

Board-Level prototype validation: a Built-in controller and extended BS architecture

Gustavo Costa Alves (Author) (Other); Telmo Pedro Gomes Amaral (Author) (FEUP); José Martins Ferreira (Author) (FEUP)

1999

Scientific classification Documents

File name	Description	Size
35.C-ISCAS_1999_53932	Board-Level Prototype Validation: A Built-In Controller and Extended BS Architecture	375.30 KB

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