From circuit simulation to circuit verification: an internal+boundary-scan-based solution

• Type: Article in International Conference Proceedings Book
• Date: 2000

Authors

Gustavo Costa Alves (Author) Other; Marcelo Lubaszewski (Author) Other; Margrit Krug (Author) Other; José Martins Ferreira (Author) FEUP

Conference proceedings International

Title: Proceedings of the European Test Workshop ETW'00

Pages: 1-3

European Test Workshop ETW¿00

Cascais, Portugal, 23 a 26 de Maio de 2000

Scientific classification

CORDIS: Technological sciences > Engineering > Electrical engineering

FOS: Engineering and technology > Electrical engineering, Electronic engineering, Information engineering

Other information

Abstract (EN): Matching the results obtained from circuit simulation with those extracted from circuit functioning is a common stage of the final verification process. Many current verification techniques use the I/O vectors produced during functional and / or timing simulation, for creating the test vectors to be applied / compared against the circuit responses. Techniques that are more complete include extracting the values of internal sequential nodes and comparing these using internal scans. This paper describes such a solution for verifying digital designs implemented in currently commercial available CPLDs. The test program encompasses the design and development phase, namely: the file containing the results from simulation, the BSDL file, an internal scan chain description file, and one file containing the user options.

Language: English

Type (Professor's evaluation): Scientific

No. of pages: 3