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DRAFT: An On-line Concurrent Test for Partial and Dynamically Reconfigurable FPGAs

Title
DRAFT: An On-line Concurrent Test for Partial and Dynamically Reconfigurable FPGAs
Type
Article in International Conference Proceedings Book
Year
2001
Authors
Manuel Gericota
(Author)
Other
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Gustavo Costa Alves
(Author)
Other
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Miguel L. Silva
(Author)
Other
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José Martins Ferreira
(Author)
FEUP
Conference proceedings International
Pages: 553-558
Design of Circuits and Integrated Systems conference DCIS¿01
Porto, Portugal, 20 a 23 de Novembro de 2001
Scientific classification
CORDIS: Technological sciences > Engineering > Electrical engineering
FOS: Engineering and technology > Electrical engineering, Electronic engineering, Information engineering
Other information
Abstract (EN): The use of partial and dynamically reconfigurable FPGAs in reconfigurable systems opens exciting possibilities, since they enable the concurrent reconfiguration of part of the system without interrupting its operation. Nevertheless, larger dies and the use of smaller submicron scales in the manufacturing of this new kind of FPGAs increase the probability of failures after many reconfiguration processes. New methods of test and fault tolerance are therefore required, capable of ensuring system reliability. This paper presents improvements to our RaT Freed Resources technique, a structural concurrent test approach able to detect and diagnose faults without disturbing system operation, throughout its lifetime.
Language: English
Type (Professor's evaluation): Scientific
No. of pages: 6
License type: Click to view license CC BY-NC
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50.C-DCIS_2001_69352 DRAFT: An On-line Concurrent Test for Partial and Dynamically Reconfigurable FPGAs 169.21 KB
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DRAFT: An On-line Fault Detection Method for Dynamic and Partially Reconfigurable FPGAs (2001)
Article in International Conference Proceedings Book
Manuel Gericota; Gustavo Costa Alves; Miguel L. Silva; José Martins Ferreira
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