Parallel Implementation of K-Means Algorithm on FPGA

• Tipo: Artigo em Revista Científica Internacional
• Data: 2020

Autores

Leonardo A. Dias (Autor) Outra; João Canas Ferreira (Autor) FEUP; Marcelo A. Fernandes (Autor) Outra

Revista

Título: IEEE Access

Vol. 8

Páginas: 41071-41084

ISSN: 2169-3536

Editora: IEEE

Indexação

ISI Web of Knowledge - 1 Citação

Scopus - 2 Citações

Outras Informações

ID Authenticus: P-00R-WWM

DOI: 10.1109/access.2020.2976900

Abstract (EN): The K-means algorithm is widely used to find correlations between data in different application domains. However, given the massive amount of data stored, known as Big Data, the need for high-speed processing to analyze data has become even more critical, especially for real-time applications. A solution that has been adopted to increase the processing speed is the use of parallel implementations on FPGA, which has proved to be more efficient than sequential systems. Hence, this paper proposes a fully parallel implementation of the K-means algorithm on FPGA to optimize the system & x2019;s processing time, thus enabling real-time applications. This proposal, unlike most implementations proposed in the literature, even parallel ones, do not have sequential steps, a limiting factor of processing speed. Results related to processing time (or throughput) and FPGA area occupancy (or hardware resources) were analyzed for different parameters, reaching performances higher than 53 millions of data points processed per second. Comparisons to the state of the art are also presented, showing speedups of more than over a partially serial implementation.

Idioma: Inglês

Tipo (Avaliação Docente): Científica

Nº de páginas: 14