High Level Language Specification of TPG Procedures for F-BST Boards, relatório D4.2

• Tipo: Relatório Técnico
• Data: 1990

Autores

José Martins Ferreira (Autor) FEUP; José Silva Matos (Autor) FEUP; F. Jong (Autor) Outra

Classificação Científica

CORDIS: Ciências Tecnológicas > Engenharia > Engenharia electrotécnica

FOS: Ciências da engenharia e tecnologias > Engenharia electrotécnica, electrónica e informática

Outras Informações

Abstract (EN): This document presents a high level pseudocode specification of a set of test pattern generation (TPG) procedures for testing interconnects in boards loaded exclusively with BST components, where more than one BST chain may exist. The characteristics of the adopted board-level fault model are briefly described. Open, stuck-at and short faults are considered, and the underlying technology related assumptions are presented. For interconnect short testing, a two-step algorithm is presented. In the first step, a minimum size set of test patterns (TPs) with full fault detection capability is used. The concept of Eventually Puzzling Syndromes is introduced and is used to specify a reduced complexity second step, allowing complete fault location. The TPG procedures for detection and diagnosis of the various fault types are presented in a high level C language type pseudocode.

Idioma: Português

Tipo (Avaliação Docente): Científica

Nº de páginas: 31