Test Pattern Generation Methodology for Full Boundary Scan Test, relatório D4.1

• Tipo: Relatório Técnico
• Data: 1989

Autores

José Martins Ferreira (Autor) FEUP; José Silva Matos (Autor) FEUP; F. Jong (Autor) Outra

Classificação Científica

CORDIS: Ciências Tecnológicas > Engenharia > Engenharia electrotécnica

FOS: Ciências da engenharia e tecnologias > Engenharia electrotécnica, electrónica e informática

Outras Informações

Abstract (EN): This document describes the test pattern generation (TPG) methodology for boards loaded exclusively with BST components. A domain definition is presented in first place, followed by a discussion of the constraints leading to the definition of the adopted fault model. The various problems affecting fault diagnosis are exemplified and their influence on the TPG algorithms is outlined. An overview of TPG algorithms for interconnect fault detection and diagnosis is then presented. Their complexity and relative merits concerning diagnostic accuracy are discussed. Test application times for a typical F-BST board are also considered. The choice of a TPG algorithm to use within the scope of this work is finally made and a formal specification for all its various steps is presented.

Idioma: Português

Tipo (Avaliação Docente): Científica

Nº de páginas: 61