Publications

Publications with the same authors as the Concurrent replication of active logic blocks: a core solution for online testing and logic space defragmentation in reconfigurable systems publication

Group by: Tipo Ano Order: Title Year Type of publication

Chapter or Part of a Book

Run-time Defragmentation for Dynamically Reconfigurable Hardware

Manuel G. Gericota (Author) (Other); Gustavo R. Alves (Author) (Other); Miguel L. Silva (Author) (Other); José M. Ferreira (Author) (FEUP)

2005

Scientific classification

FOS: Electrical engineering, Electronic engineering, Information engineering

Article in International Scientific Journal

Reliability and availability in reconfigurable computing: A basis for a common solution

Manuel G. Gericota (Author) (Other); Gustavo R. Alves (Author) (Other); Miguel L. Silva (Author) (Other); José M. Ferreira (Author) (FEUP)

2008

Scientific classification Indexing Documents

ISI Web of Science

Scopus

INSPEC

FOS: Electrical engineering, Electronic engineering, Information engineering

File name	Description	Size
5.J-ToVLSIS_2008_59326	Reliability and Availability in Reconfigurable Computing: A Basis for a Common Solution	1446.79 KB

Article in International Conference Proceedings Book

Run-time management of logic resources on reconfigurable systems

Manuel G. Gericota (Author) (Other); Gustavo R. Alves (Author) (Other); Miguel L. Silva (Author) (Other); José M. Ferreira (Author) (FEUP)

2003

Scientific classification Indexing Documents

ISI Web of Science

Scopus

INSPEC

FOS: Electrical engineering, Electronic engineering, Information engineering

File name	Description	Size
60.C-DATE_2003_58728	Run-Time Management of Logic Resources on Reconfigurable Systems	364.54 KB

Programmable logic devices: a test approach for the Input / Output blocks and Pad-to-Pin interconnections

Manuel G. Gericota (Author) (Other); Gustavo R. Alves (Author) (Other); Miguel L. Silva (Author) (Other); José M. Ferreira (Author) (FEUP)

2003

Scientific classification Documents

FOS: Electrical engineering, Electronic engineering, Information engineering

File name	Description	Size
59.C-LATW_2003_58727	Programmable Logic Devices: A Test Approach for the Input / Output Blocks and Pad-to-Pin Interconnections	354.19 KB

DRAFT: A scanning test methodology for dynamic and partially reconfigurable FPGAs

Manuel G. Gericota (Author) (Other); Gustavo R. Alves (Author) (Other); Miguel L. Silva (Author) (Other); José M. Ferreira (Author) (FEUP)

2001

Scientific classification Documents

CORDIS: Electrical engineering

FOS: Electrical engineering, Electronic engineering, Information engineering

File name	Description	Size
47.C-ETW_2001_65724	DRAFT: A Scanning Test Methodology for Dynamic and Partially Reconfigurable FPGAs	157.80 KB

A novel methodology for the concurrent test of partial and dynamically reconfigurable SRAM-based FPGAs

Manuel G. Gericota (Author) (Other); Gustavo R. Alves (Author) (Other); Miguel L. Silva (Author) (Other); José M. Ferreira (Author) (FEUP)

2002

Scientific classification Indexing Documents

ISI Web of Science

Scopus

INSPEC

FOS: Electrical engineering, Electronic engineering, Information engineering

CORDIS: Electrical engineering

File name	Description	Size
10.P-DATE_2002_66138	A novel methodology for the concurrent test of partial and dynamically reconfigurable SRAM-based FPGAs	121.33 KB

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