Test Methodology for Full Boundary Scan Test, relatório R4.1

• Type: Technical Report
• Date: 1989

Authors

F. Jong (Author) Other; José Martins Ferreira (Author) FEUP

Scientific classification

CORDIS: Technological sciences > Engineering > Electrical engineering

FOS: Engineering and technology > Electrical engineering, Electronic engineering, Information engineering

Other information

Abstract (EN): In this first report on subtask 4.1, an introduction is given to the general concepts of testing digital circuits. This testing primarily focuses on volume production. The introduction indicates the need for structural testing during production of digital circuits. The principle of Boundary Scan Test (BST), as described in the JTAG V2.0 document, is studied for its applicability in several areas of testing. Also the hierarchical structures encountered in systems are studied. The principal discussions are relevant for a wide range of digital products but the remainder of this report mainly deals with board level tests. To be able to use BST, one has to understand the circuitry under test. The possible faults that can occur are therefore modelled in the second chapter, before deriving a strategy that will detect all possible faults. Also the technology dependency that gives problems in fault detection is discussed. Finally, in the last chapter, the actual protocol for testing with full BST is given, starting with testing the on-board BST infrastructure itself. This chapter shows the BST test sequence to be followed and gives an idea about the test times involved.

Language: Portuguese

Type (Professor's evaluation): Scientific

No. of pages: 51