Verification of TPG Procedures for BST Boards with Additional ST-Clusters, relatório R4.4

• Type: Technical Report
• Date: 1992

Authors

José Martins Ferreira (Author) FEUP; José Silva Matos (Author) FEUP; F. Jong (Author) Other

Scientific classification

CORDIS: Technological sciences > Engineering > Electrical engineering

FOS: Engineering and technology > Electrical engineering, Electronic engineering, Information engineering

Other information

Abstract (EN): Report R4.4 presents the verification of TPG procedures for BST boards where additional (simple-to-test) clusters of non-BST components may be present. These clusters are restricted to low-complexity combinational blocks of logic (and eventually low-depth sequential circuits) and to regular structure blocks, like RAM or ROM memories. This document results from the work done in task 4.2.3 and is related to the work described in report R4.2 and in deliverables D4.4, D4.7 and D4.11.

Language: Portuguese

Type (Professor's evaluation): Scientific

No. of pages: 54