On combining temporal partitioning and sharing of functional units in compilation for reconfigurable architectures

• Type: Article in International Scientific Journal
• Date: 2003

Authors

João M. P. Cardoso (Author) FEUP

Journal

Title: IEEE Transactions on Computers

Vol. 52 No. 10

Pages: 1362-1375

ISSN: 0018-9340

Publisher: IEEE

Indexing

ISI Web of Knowledge - 34 Citations

Scopus - 45 Citations

Scientific classification

FOS: Engineering and technology > Electrical engineering, Electronic engineering, Information engineering

Other information

Authenticus ID: P-000-EZG

DOI: 10.1109/tc.2003.1234532

Abstract (EN): Resource virtualization on FPGA devices, achievable due to its dynamic reconfiguration capabilities, provides an attractive solution to save silicon area. Architectural synthesis for dynamically reconfigurable FPGA-based digital systems needs to consider the case of reducing the number of temporal partitions (reconfigurations) by enabling sharing of some functional units in the same temporal partition. This paper proposes a novel algorithm for automated datapath design from behavioral input descriptions (represented by an acyclic dataflow graph), which simultaneously performs temporal partitioning and sharing of functional units. The proposed algorithm attempts to minimize both the number of temporal partitions and the execution latency of the generated solution. Temporal partitioning, resource sharing, scheduling, and a simple form of allocation and binding are all integrated in a single task. The algorithm is based on heuristics and on a new concept of construction by gradually enlarging timing slots. Results show the efficiency and effectiveness of the algorithm when compared to existent approaches.

Language: English

Type (Professor's evaluation): Scientific

No. of pages: 14