On combining temporal partitioning and sharing of functional units in compilation for reconfigurable architectures

• Tipo: Artigo em Revista Científica Internacional
• Data: 2003

Autores

João M. P. Cardoso (Autor) FEUP

Revista

Título: IEEE Transactions on Computers

Vol. 52 Nº 10

Páginas: 1362-1375

ISSN: 0018-9340

Editora: IEEE

Indexação

ISI Web of Knowledge - 34 Citações

Scopus - 45 Citações

Classificação Científica

FOS: Ciências da engenharia e tecnologias > Engenharia electrotécnica, electrónica e informática

Outras Informações

ID Authenticus: P-000-EZG

DOI: 10.1109/tc.2003.1234532

Abstract (EN): Resource virtualization on FPGA devices, achievable due to its dynamic reconfiguration capabilities, provides an attractive solution to save silicon area. Architectural synthesis for dynamically reconfigurable FPGA-based digital systems needs to consider the case of reducing the number of temporal partitions (reconfigurations) by enabling sharing of some functional units in the same temporal partition. This paper proposes a novel algorithm for automated datapath design from behavioral input descriptions (represented by an acyclic dataflow graph), which simultaneously performs temporal partitioning and sharing of functional units. The proposed algorithm attempts to minimize both the number of temporal partitions and the execution latency of the generated solution. Temporal partitioning, resource sharing, scheduling, and a simple form of allocation and binding are all integrated in a single task. The algorithm is based on heuristics and on a new concept of construction by gradually enlarging timing slots. Results show the efficiency and effectiveness of the algorithm when compared to existent approaches.

Idioma: Inglês

Tipo (Avaliação Docente): Científica

Nº de páginas: 14