Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems

• Tipo: Artigo em Revista Científica Internacional
• Data: 2013

Autores

João Bispo (Autor) Outra; Nuno Paulino (Autor) FEUP; João Cardoso (Autor) FEUP; João Canas Ferreira (Autor) FEUP

Revista

Título: IEEE Transactions on Industrial Informatics

Vol. 9 Nº 3

Páginas: 1625-1634

ISSN: 1551-3203

Editora: IEEE

Indexação

ISI Web of Knowledge - 9 Citações

Scopus - 11 Citações

INSPEC

Classificação Científica

FOS: Ciências da engenharia e tecnologias > Engenharia electrotécnica, electrónica e informática

CORDIS: Ciências Tecnológicas > Engenharia > Engenharia de computadores ; Ciências Tecnológicas > Engenharia > Engenharia electrónica

Outras Informações

ID Authenticus: P-006-8H5

DOI: 10.1109/tii.2012.2235844

Abstract (EN): This paper presents a novel approach to accelerate program execution by mapping repetitive traces of executed instructions, called Megablocks, to a runtime reconfigurable array of functional units. An offline tool suite extracts Megablocks from microprocessor instruction traces and generates a Reconfigurable Processing Unit (RPU) tailored for the execution of those Megablocks. The system is able to transparently movebcomputations from the microprocessor to the RPU at runtime. A prototype implementation of the system using a cacheless MicroBlaze microprocessor running code located in external memory reaches speedups from 2.2x to 18.2x for a set of 14 benchmark kernels. For a system setup which maximizes microprocessor performance by having the application code located in internal block RAMs, speedups from 1.4x to 2.8x were estimated.

Idioma: Inglês

Tipo (Avaliação Docente): Científica

Nº de páginas: 10