From Instruction Traces to Specialized Reconfigurable Arrays

• Tipo: Artigo em Livro de Atas de Conferência Internacional
• Data: 2011

Autores

João Bispo (Autor) Outra; Nuno Paulino (Autor) FEUP; João M. P. Cardoso (Autor) FEUP; João Canas Ferreira (Autor) FEUP

Ata de Conferência Internacional

Título: 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011, Cancun, Mexico, November 30 - December 2, 2011

Páginas: 386-391

2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011

Cancun, Quintana Roo, 30 November 2011 through 2 December 2011

Indexação

Scopus - 9 Citações

Classificação Científica

FOS: Ciências da engenharia e tecnologias > Engenharia electrotécnica, electrónica e informática

CORDIS: Ciências Tecnológicas > Engenharia > Engenharia electrónica ; Ciências Tecnológicas > Engenharia > Engenharia de computadores

Outras Informações

ID Authenticus: P-008-2EE

DOI: 10.1109/ReConFig.2011.43

Abstract (EN): This paper presents an offline tool-chain which automatically extracts loops (Mega blocks) from Micro Blaze instruction traces and creates a tailored Reconfigurable Processing Unit (RPU) for those loops. The system moves loops from the CPU to the RPU transparently, at runtime, and without changing the executable binaries. The system was implemented in an FPGA and for the tested kernels measured speedups ranged between 3.9x and 18.2x for a Micro Blaze CPU without cache. We estimate speedups from 1.03x to 2.01x, when comparing to the best estimated performance achieved with a single Micro Blaze. © 2011 IEEE.

Idioma: Inglês

Tipo (Avaliação Docente): Científica