Creation of Partial FPGA Configurations at Run-Time

• Tipo: Artigo em Livro de Atas de Conferência Internacional
• Data: 2010

Autores

Silva, ML (Autor) Outra; João Canas Ferreira (Autor) FEUP

Ata de Conferência Internacional

Título: Proceedings - 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2010

Páginas: 80-87

13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2010

Lille, 1 September 2010 through 3 September 2010

Indexação

ISI Web of Knowledge - 3 Citações

Scopus - 5 Citações

Classificação Científica

FOS: Ciências da engenharia e tecnologias > Engenharia electrotécnica, electrónica e informática

CORDIS: Ciências Tecnológicas > Engenharia > Engenharia de computadores ; Ciências Tecnológicas > Engenharia > Engenharia electrónica

Outras Informações

ID Authenticus: P-007-WFR

DOI: 10.1109/dsd.2010.14

Abstract (EN): This paper describes and evaluates a method to generate partial FPGA configurations at run-time. The proposed technique is aimed at adaptive embedded systems that employ run-time reconfiguration to achieve high flexibility and performance. The approach is based on the availability of a library of partial bitstreams for a set of basic components. New partial configurations for circuits defined by netlists of basic components are created by merging together a default bitstream of the target area, the relocated configurations of the components, and the configurations of the switch matrices used for building the connections between the components. An implementation targeting the Virtex-II Pro platform FPGA is described. It runs on the embedded 300MHz PowerPC CPU present in the FPGA. The proof-of-concept implementation was used to create partial configurations at run-time for 20 circuits with up to 21 components and 288 connections. The complete configuration creation process took between 7s and 97 s.

Idioma: Inglês

Tipo (Avaliação Docente): Científica

Nº de páginas: 8