Algorithms for run-time placement and routing on Virtex II Pro FPGAs

• Tipo: Artigo em Livro de Atas de Conferência Nacional
• Data: 2010

Autores

Miguel L. Silva (Autor) FEUP; João Canas Ferreira (Autor) FEUP

Ata de Conferência Nacional

Título: Actas das VI Jornadas sobre Sistemas Reconfiguráveis - REC'2010

Páginas: 9-16

VI Jornadas sobre Sistemas Reconfiguráveis (REC'2010)

Aveiro, 4 a 5 de Fevereiro, 2010

Classificação Científica

FOS: Ciências da engenharia e tecnologias > Engenharia electrotécnica, electrónica e informática

CORDIS: Ciências Tecnológicas > Engenharia > Engenharia de computadores ; Ciências Tecnológicas > Engenharia > Engenharia electrónica

Outras Informações

Abstract (EN): Run-time reconfiguration is a useful approach to the implementation of highly-adaptive embedded systems. To generate partial bitstreams at run-time for dynamic reconfiguration of sections of a platform FPGA we combine partial bitstreams of coarse-grained components specified by an acyclic netlist. The placement an routing algorithm play and essential role on the generation of partial bitstreams. A greedy placement heuristic based on topological sorting is used to determine the positions of individual components, and a router based on non-backtracking search over restricted areas determines the routes for the interconnections. The approach is validated with a set of 35 benchmarks (both synthetic and application-derived) having between three and 41 components, the complete process of bitstream generation takes between 7s and 101s (average 48.3s) when running on an embedded PowerPC 405 microprocessor clocked at 300MHz.

Idioma: Inglês

Tipo (Avaliação Docente): Científica

Nº de páginas: 8