Run-time Generation of Partial Configurations for Arithmetic Expressions

• Tipo: Artigo em Livro de Atas de Conferência Internacional
• Data: 2010

Autores

Miguel L. Silva (Autor) FEUP; João Canas Ferreira (Autor) FEUP; Miguel L. Silva (Autor) FEUP

Ata de Conferência Internacional

Título: 53RD IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS

Páginas: 117-120

53rd Midwest Symposium on Circuits and Systems (MWSCAS 2010)

Seattle, WA, AUG 01-04, 2010

Indexação

ISI Proceedings

ISI Web of Knowledge - 2 Citações

Scopus - 0 Citações

Classificação Científica

FOS: Ciências da engenharia e tecnologias > Engenharia electrotécnica, electrónica e informática

CORDIS: Ciências Tecnológicas > Engenharia > Engenharia electrónica ; Ciências Tecnológicas > Engenharia > Engenharia de computadores

Outras Informações

ID Authenticus: P-003-DG5

DOI: 10.1109/mwscas.2010.5548575

Abstract (EN): Adaptive embedded systems can achieve enhanced flexibility by performing run-time reconfiguration of hardware. This paper describes a method to generate at run-time new partial FPGA configurations corresponding to arithmetic expressions. This is achieved by merging available partial bitstreams of arithmetic components to produce a new partial bitstream for a specific FPGA area. The connections among the components are mapped to the switch matrices of the reconfigurable fabric, and the corresponding information is added to the new partial configuration. The proposed method was implemented for a Virtex-II Pro FPGA with a 300 MHz PowerPC 405 CPU. It was used to create partial configurations in less than 69 s for sets of arithmetic circuits with up to 25 components and 208 connections.

Idioma: Inglês

Tipo (Avaliação Docente): Científica

Nº de páginas: 4