Verification of TPG Procedures for BST Boards with Additional ST-Clusters, relatório R4.4

• Tipo: Relatório Técnico
• Data: 1992

Autores

José Martins Ferreira (Autor) FEUP; José Silva Matos (Autor) FEUP; F. Jong (Autor) Outra

Classificação Científica

CORDIS: Ciências Tecnológicas > Engenharia > Engenharia electrotécnica

FOS: Ciências da engenharia e tecnologias > Engenharia electrotécnica, electrónica e informática

Outras Informações

Abstract (EN): Report R4.4 presents the verification of TPG procedures for BST boards where additional (simple-to-test) clusters of non-BST components may be present. These clusters are restricted to low-complexity combinational blocks of logic (and eventually low-depth sequential circuits) and to regular structure blocks, like RAM or ROM memories. This document results from the work done in task 4.2.3 and is related to the work described in report R4.2 and in deliverables D4.4, D4.7 and D4.11.

Idioma: Português

Tipo (Avaliação Docente): Científica

Nº de páginas: 54