Publications

Publications with the same authors as the Generation of Customized Accelerators for Loop Pipelining of Binary Instruction Traces publication

Group by: Tipo Ano Order: Title Year Type of publication

Article in International Scientific Journal

Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems

João Bispo (Author) (Other); Nuno Paulino (Author) (FEUP); João Cardoso (Author) (FEUP); João Canas Ferreira (Author) (FEUP)

2013

Scientific classification Indexing

ISI Web of Knowledge - 9 Citations

Scopus - 11 Citations

INSPEC

FOS: Electrical engineering, Electronic engineering, Information engineering

CORDIS: Computer engineering ; Electronic engineering

Transparent runtime migration of loop-based traces of processor instructions to reconfigurable processing units

João Bispo (Author) (Other); Nuno Paulino (Author) (FEUP); João Cardoso (Author) (FEUP); João Canas Ferreira (Author) (FEUP)

2013

Scientific classification Indexing

Scopus - 7 Citations

INSPEC

FOS: Electrical engineering, Electronic engineering, Information engineering

CORDIS: Computer engineering

Optimizing OpenCL Code for Performance on FPGA: k-Means Case Study With Integer Data Sets

Nuno Paulino (Author) (FEUP); João Canas Ferreira (Author) (FEUP); João M. P. Cardoso (Author) (FEUP)

2020

Indexing

ISI Web of Knowledge - 3 Citations

Scopus - 5 Citations

Improving Performance and Energy Consumption in Embedded Systems via Binary Acceleration: A Survey

Nuno Paulino (Author) (FEUP); João Canas Ferreira (Author) (FEUP); João M. P. Cardoso (Author) (FEUP)

2020

Indexing

ISI Web of Knowledge - 10 Citations

Scopus - 12 Citations

Dynamic Partial Reconfiguration of Customized Single-Row Accelerators

Nuno Paulino (Author) (FEUP); João Canas Ferreira (Author) (FEUP); João M. P. Cardoso (Author) (FEUP)

2019

Indexing

ISI Web of Knowledge - 6 Citations

Scopus - 7 Citations

INSPEC

A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses

Nuno Paulino (Author) (Other); João Canas Ferreira (Author) (FEUP); João M. P. Cardoso (Author) (FEUP)

2015

Indexing

ISI Web of Knowledge - 2 Citations

Scopus - 4 Citations

A Binary Translation Framework for Automated Hardware Generation

Nuno Paulino (Author) (FEUP); João Bispo (Author) (FEUP); João Canas Ferreira (Author) (FEUP); João M. P. Cardoso (Author) (FEUP)

2021

Indexing

ISI Web of Knowledge - 2 Citations

Scopus - 2 Citations

Article in International Conference Proceedings Book

Transparent Acceleration of Program Execution Using Reconfigurable Hardware

Nuno Paulino (Author) (Other); João Canas Ferreira (Author) (FEUP); João Bispo (Author) (FEUP); João M. P. Cardoso (Author) (FEUP)

2015

Indexing

ISI Web of Knowledge - 8 Citations

Scopus - 8 Citations

Trace-Based Reconfigurable Acceleration with Data Cache and External Memory Support

Nuno Paulino (Author) (Other); João Canas Ferreira (Author) (FEUP); João M. P. Cardoso (Author) (FEUP)

2014

Indexing

ISI Web of Knowledge - 6 Citations

Scopus - 5 Citations

On the Performance Effect of Loop Trace Window Size on Scheduling for Configurable Coarse Grain Loop Accelerators

Santos, T (Author) (Other); Nuno Paulino (Author) (FEUP); João Bispo (Author) (FEUP); João M. P. Cardoso (Author) (FEUP); João Canas Ferreira (Author) (FEUP)

2021

Indexing

ISI Web of Knowledge

Scopus

From Instruction Traces to Specialized Reconfigurable Arrays

João Bispo (Author) (Other); Nuno Paulino (Author) (FEUP); João M. P. Cardoso (Author) (FEUP); João Canas Ferreira (Author) (FEUP)

2011

Scientific classification Indexing

Scopus - 9 Citations

FOS: Electrical engineering, Electronic engineering, Information engineering

CORDIS: Electronic engineering ; Computer engineering

Executing ARMv8 Loop Traces on Reconfigurable Accelerator via Binary Translation Framework

Nuno Paulino (Author) (FEUP); João Canas Ferreira (Author) (FEUP); João Bispo (Author) (FEUP); João M. P. Cardoso (Author) (FEUP)

2020

Indexing

ISI Web of Knowledge

Scopus

INSPEC

Records 1 to 12 from 12

 

1