From Instruction Traces to Specialized Reconfigurable Arrays

• Type: Article in International Conference Proceedings Book
• Date: 2011

Authors

João Bispo (Author) Other; Nuno Paulino (Author) FEUP; João M. P. Cardoso (Author) FEUP; João Canas Ferreira (Author) FEUP

Conference proceedings International

Title: 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011, Cancun, Mexico, November 30 - December 2, 2011

Pages: 386-391

2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011

Cancun, Quintana Roo, 30 November 2011 through 2 December 2011

Indexing

Scopus - 9 Citations

Scientific classification

FOS: Engineering and technology > Electrical engineering, Electronic engineering, Information engineering

CORDIS: Technological sciences > Engineering > Electronic engineering ; Technological sciences > Engineering > Computer engineering

Other information

Authenticus ID: P-008-2EE

DOI: 10.1109/ReConFig.2011.43

Abstract (EN): This paper presents an offline tool-chain which automatically extracts loops (Mega blocks) from Micro Blaze instruction traces and creates a tailored Reconfigurable Processing Unit (RPU) for those loops. The system moves loops from the CPU to the RPU transparently, at runtime, and without changing the executable binaries. The system was implemented in an FPGA and for the tested kernels measured speedups ranged between 3.9x and 18.2x for a Micro Blaze CPU without cache. We estimate speedups from 1.03x to 2.01x, when comparing to the best estimated performance achieved with a single Micro Blaze. © 2011 IEEE.

Language: English

Type (Professor's evaluation): Scientific