Executing ARMv8 Loop Traces on Reconfigurable Accelerator via Binary Translation Framework

• Type: Article in International Conference Proceedings Book
• Date: 2020

Authors

Nuno Paulino (Author) FEUP; João Canas Ferreira (Author) FEUP; João Bispo (Author) FEUP; João M. P. Cardoso (Author) FEUP

Conference proceedings International

Title: 30th International Conference on Field-Programmable Logic and Applications, FPL 2020, Gothenburg, Sweden, August 31 - September 4, 2020

Pages: 367-367

Indexing

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Other information

Authenticus ID: P-00S-V1M

DOI: 10.1109/FPL50879.2020.00072

Abstract (EN): Performance and power efficiency in edge and embedded systems can benefit from specialized hardware. To avoid the effort of manual hardware design, we explore the generation of accelerator circuits from binary instruction traces for several Instruction Set Architectures. © 2020 IEEE.

Language: English

Type (Professor's evaluation): Scientific

No. of pages: 1