Resumo (PT):
Abstract (EN):
Performance and power efficiency in edge and embedded systems can benefit from specialized hardware. To avoid the effort of manual hardware design, we explore the generation of accelerator circuits from binary instruction traces for several Instruction Set Architectures. © 2020 IEEE.
Idioma:
Inglês
Tipo (Avaliação Docente):
Científica
Nº de páginas:
1