A Binary Translation Framework for Automated Hardware Generation

• Type: Article in International Scientific Journal
• Date: 2021

Authors

Nuno Paulino (Author) FEUP; João Bispo (Author) FEUP; João Canas Ferreira (Author) FEUP; João M. P. Cardoso (Author) FEUP

Journal

Title: IEEE Micro

Vol. 41

Pages: 15-22

ISSN: 0272-1732

Publisher: IEEE

Indexing

ISI Web of Knowledge - 2 Citations

Scopus - 2 Citations

Other information

Authenticus ID: P-00V-2EW

DOI: 10.1109/mm.2021.3088670

Abstract (EN): As applications move to the edge, efficiency in computing power and power/energy consumption is required. Heterogeneous computing promises to meet these requirements through application-specific hardware accelerators. Runtime adaptivity might be of paramount importance to realize the potential of hardware specialization, but further study is required on workload retargeting and offloading to reconfigurable hardware. This article presents our framework for the exploration of both offloading and hardware generation techniques. The framework is currently able to process instruction sequences from MicroBlaze, ARMv8, and riscv32imaf binaries, and to represent them as Control and Dataflow Graphs for transformation to implementations of hardware modules. We illustrate the framework's capabilities for identifying binary sequences for hardware translation with a set of 13 benchmarks.

Language: English

Type (Professor's evaluation): Scientific

No. of pages: 8