A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses

• Type: Article in International Scientific Journal
• Date: 2015

Authors

Nuno Paulino (Author) Other; João Canas Ferreira (Author) FEUP; João M. P. Cardoso (Author) FEUP

Journal

Title: ACM Transactions on Reconfigurable Technology and Systems

Vol. 7

Pages: 29:1-29:20

ISSN: 1936-7406

Publisher: ACM

Indexing

ISI Web of Knowledge - 2 Citations

Scopus - 4 Citations

Other information

Authenticus ID: P-00A-4B4

DOI: 10.1145/2629468

Abstract (EN): This article presents a reconfigurable hardware/software architecture for binary acceleration of embedded applications. A Reconfigurable Processing Unit (RPU) is used as a coprocessor of the General Purpose Processor (GPP) to accelerate the execution of repetitive instruction sequences called Megablocks. A toolchain detects Megablocks from instruction traces and generates customized RPU implementations. The implementation of Megablocks with memory accesses uses a memory-sharing mechanism to support concurrent accesses to the entire address space of the GPP's data memory. The scheduling of load/store operations and memory access handling have been optimized to minimize the latency introduced by memory accesses. The system is able to dynamically switch the execution between the GPP and the RPU when executing the original binaries of the input application. Our proof-of-concept prototype achieved geometric mean speedups of 1.60x and 1.18x for, respectively, a set of 37 benchmarks and a subset considering the 9 most complex benchmarks. With respect to a previous version of our approach, we achieved geometric mean speedup improvements from 1.22 to 1.53 for the 10 benchmarks previously used.

Language: English

Type (Professor's evaluation): Scientific

No. of pages: 20