Boundary scan test, test methodology, and fault modeling

• Tipo: Artigo em Revista Científica Internacional
• Data: 1991

Autores

Frans de Jong (Autor) Outra; José S. Matos (Autor) FEUP; José M. Ferreira (Autor) FEUP

Revista

Título: Journal of Electronic Testing: Theory and Applications (JETTA)

Vol. 2 Nº 1

Páginas: 77-88

ISSN: 0923-8174

Editora: Springer Nature

Indexação

Scopus

INSPEC

Classificação Científica

FOS: Ciências da engenharia e tecnologias > Engenharia electrotécnica, electrónica e informática

CORDIS: Ciências Tecnológicas > Engenharia > Engenharia electrotécnica

Outras Informações

Abstract (EN): The test technique called "boundary scan test" (BST) offers new opportunities in testing but confronts users with new problems too. The implementation of BST in a chip has become an IEEE standard and users on board level are the next group to begin thinking about using the new possibilities. This article addresses some of the questions about changes in board-level testing and fault diagnosis. The fault model itself is also affected by using BST. Trivial items are extended with more sophisticated details in order to complete the fault model. Finally, BST appears to be a test technique that offers a high degree of detectability on board level, but for diagnosis, some additional effort has to be made.

Idioma: Inglês

Tipo (Avaliação Docente): Científica

Nº de páginas: 12