Transparent Control Flow Transfer between CPU and Accelerators for HPC

• Tipo: Artigo em Revista Científica Internacional
• Data: 2021

Autores

Daniel Granhão (Autor) Outra; João Canas Ferreira (Autor) FEUP

Revista

Título: Electronics (Switzerland)

Vol. 10

Páginas: 1-12

ISSN: 2079-9292

Editora: MDPI

Indexação

ISI Web of Knowledge - 1 Citação

Scopus - 1 Citação

Outras Informações

ID Authenticus: P-00T-DEC

DOI: 10.3390/electronics10040406

Abstract (EN): Heterogeneous platforms with FPGAs have started to be employed in the High-Performance Computing (HPC) field to improve performance and overall efficiency. These platforms allow the use of specialized hardware to accelerate software applications, but require the software to be adapted in what can be a prolonged and complex process. The main goal of this work is to describe and evaluate mechanisms that can transparently transfer the control flow between CPU and FPGA within the scope of HPC. Combining such a mechanism with transparent software profiling and accelerator configuration could lead to an automatic way of accelerating regular applications. In this work, a mechanism based on the ptrace system call is proposed, and its performance on the Intel Xeon+FPGA platform is evaluated. The feasibility of the proposed approach is demonstrated by a working prototype that performs the transparent control flow transfer of any function call to a matching hardware accelerator. This approach is more general than shared library interposition at the cost of a small time overhead in each accelerator use (about 1.3 ms in the prototype implementation).

Idioma: Inglês

Tipo (Avaliação Docente): Científica

Nº de páginas: 12