Computer Architecture

Code:

L.EIC006

Acronym:

AC

Keywords
Classification	Keyword
OFICIAL	Informatics Engineering and Computing

Instance: 2023/2024 - 2S

Active?	Yes
Responsible unit:	Department of Electrical and Computer Engineering
Course/CS Responsible:	Bachelor in Informatics and Computing Engineering

Cycles of Study/Courses

Acronym	No. of Students	Study Plan	Curricular Years	Credits UCN	Credits ECTS	Contact hours	Total Time
L.EIC	554	Syllabus	1	-	6	52	162

Teaching language

Portuguese

Objectives

BACKGROUND

The architecture of a computer reflects the current technological advancement, but also sets the limits of its capabilities and performance. Variants of the ARM instruction set are used in the vast majority of current mobile platforms (tablets, cell phones). Both the system architecture and the instruction set have a profound impact on the daily practice of computer engineers.engineers.

SPECIFIC AIMS

The curricular unit "Computer Architecture" aims to develop, combine and apply in an integrated way concepts from the areas of Computer Architecture and Programming Languages. Thus, the curricular unit explores the relationship between the instruction set and low-level programming (assembly language). Mechanisms to support efficient program execution, such as instruction pipelining and jump prediction, will also be addressed. Recognizing that computer architecture goes far beyond the CPU architecture, the curricular unit will also address memory, storage and peripheral subsystems. Upon successful completion of this curricular unit, the student will have acquired the ability to identify and describe the architecture of computing platforms currently in use, as well as the ability to apply assembly programming techniques in the implementation of algorithms.

PERCENT DISTRIBUTION

• Scientific component: 60%
• Technological component: 40%

Learning outcomes and competences

After successfully completing this curricular unit, the student should be able to:

1. Explain procedure call conventions and write assembly programs.


2. Describe SIMD instructions and apply them in high-performance subroutines.


3. Describe cache memory organizations and explain their use to improve performance.


4. Explain basic instruction-level pipelining and its effect on performance.


5. Explain the mechanisms for handling data and control dependencies.


6. Describe superscalar architectures (multi-issue operation, and in-order and out-of-order execution).


7. Discuss the performance limitations of single-core processors.


8. Describe the basic organization of a symmetric multiprocessor (with multiple cores and shared memory).


9. Explain the processor's interaction with input/output (I/O) devices.


10. Evaluate the various approaches to I/O management (polling, interrupts, DMA).


11. Describe the characteristics of current secondary storage technologies and assess their impact on performance.

Working method

Presencial

Pre-requirements (prior knowledge) and co-requirements (common knowledge)

Prerequisite:

- Fundamentals of computer systems (L.EIC004): principles of assembly language programming (RISC-V) and computer organization.

Program

1. Introduction to computing platforms (CPU, memory and peripherals).


2. RISC-V architecture. Cross-language calling conventions (invocation, parameter passing).


3. SIMD instructions for explicit data parallelism.


4. Common cache memory organizations and their impact on performance.


5. Instruction level parallelism: “pipelining”; limitations; management of data and control dependencies.


6. Introduction to superscalar architectures: multiple instruction issue and out-of-order execution.


7. Limitations of single-core processors; frequency and power walls.


8. Basic organization of a “multicore” processor; cache coherence and synchronization.


9. Interfacing with peripherals: polling, interrupts, DMA.


10. Data storage subsystem (magnetic disks, solid-state drives, RAID).


11. Performance estimation of tasks that involve significant I/O activity.

Mandatory literature

David A. Patterson; Computer organization and design. ISBN: 978-0-12-820331-6 (RISC-V version,)
Bruce Jacob; Spencer W. Ng ; David T.Wang; Memory Systems - Cache, DRAM, Disk (May be accessed through the Knovel Portal)

Complementary Bibliography

Jain, A., & Lee, C; Cache Replacement Policies, Morgan & Claypool , 2019. ISBN: 9781681735764

Teaching methods and learning activities

The curricular unit has a theoretical component based on lectures about the different themes accompanied by the presentation of examples and respective discussion. Theoretical-practical sessions include the presentation, analysis and resolution of a set of questions and case studies, as well as the discussion and resolution of problems that will be tested on a computational platform or on a CPU emulator.

Software

Catapult SDK
RARS
WebRISC-V

keywords

Technological sciences > Engineering > Computer engineering

Evaluation Type

Distributed evaluation without final exam

Assessment Components

Designation	Weight (%)
Teste	100,00
Total:	100,00

Amount of time allocated to each course unit

Designation	Time (hours)
Estudo autónomo	106,00
Frequência das aulas	56,00
Total:	162,00

Eligibility for exams

To pass the course, you must meet the attendance requirements, i.e. not exceed the limit of absences from TP classes (3).

Calculation formula of final grade

To pass the course, the attendance requirements must be met.

Frequency grades from previous years are not taken into consideration.

The final grade (NF) is given by: 
NF = max(T1,T2) × 0.6 + min(T1, T2) × 0.4
where T1 and T2 are the 1st and 2nd test scores, respectively (scale 0-20).

The retake exam for approval can be global (test of 2H00) or partial (T1 or T2, 1H30 each).

Classification improvement

The course grade can be improved by taking a test on the whole subject (2h00) or a single part (1h30).