Heterogeneous Systems Architectures

Code:

M.EEC049

Acronym:

ASH

Keywords
Classification	Keyword
OFICIAL	Systems Electronics and Digital Systems

Instance: 2021/2022 - 1S

Active?	Yes
Responsible unit:	Department of Electrical and Computer Engineering
Course/CS Responsible:	Master in Electrical and Computer Engineering

Cycles of Study/Courses

Acronym	No. of Students	Study Plan	Curricular Years	Credits UCN	Credits ECTS	Contact hours	Total Time
M.EEC	6	Syllabus	2	-	6	39

Teaching language

English

Objectives

In recent decades, computer users have enjoyed the seemingly unlimited availability of transistors. Computer platforms evolved from a single processor core to multipurpose multicores and specialized cores that deliver unprecedented performance thanks to the high degree of parallelism. Recently, power efficiency has become a major issue as most emerging applications in image processing and machine learning need to perform large amounts of computation while meeting strict power and performance constraints. This has led to systems with custom computational units in the form of Field-Programmable Gate Arrays (FPGA) and other forms of reconfigurable computational units.

These trends are having a major impact on the embedded computing domain, particularly high-performance embedded computing systems. To achieve these goals, engineers are increasingly building specialized compute engines tailored to these specific tasks. The resulting computing systems are heterogeneous and contain multiple compute cores with very different execution models. Therefore, developers must understand the fundamental mapping between the application and the target computer architectures in order to fully exploit their capabilities.

Learning outcomes and competences

The course provides students with the necessary skills to:

1. Analyse the performance requirements of computational applications to design, justify and characterize solutions based on heterogeneous computing systems, involving diverse categories of general purpose processors and specialized accelerators built on FPGA, with the objective of obtaining competitive proposals against solutions built on conventional processors or homogeneous processor aggregates.


2. Develop solutions for heterogeneous computing platforms based on reconfigurable System-on-Chip devices (such as the XILINX Zynq family) with two or more integrated processor cores, making use of high level-synthesis tools and design flow for FPGAs.

Working method

Presencial

Program

1. Computing platforms: application domains, requirements, history and trends.


2. General purpose programmable platforms (CPU, GPU, MCU, DSP) and FPGA-based specialized accelerators.


3. Characterization of performance metrics: speed (throughput), power and energy consumption.


4. Communication systems between computing units: topologies, technologies and performance metrics.


5. Memory system: technologies, hierarchy, and performance metrics.


6. Quantification of software application performance by profiling.


7. Computation models and application partitioning in heterogeneous systems.


8. Application mapping for programmable “System-on-Chip” devices integrating general-purpose processors and FPGAs.


9. High-level synthesis of digital hardware for FPGA devices; optimization and design space exploration: source code transformations, loop transformations, function specialization.


10. Dynamic Hardware Reconfiguration.

Mandatory literature

Coussy, P., & Morawiec, A. ; High-Level synthesis: from algorithm to digital circuit, Springer, 2008
Terzo, O., Djemame, K., Scionti, A., & Pezuela, C. ; Heterogeneous computing architectures: challenges and vision., CRC Press, 2019
Wolf, M.; Computers as components: principles of embedded computing system design. , Elsevier/Morgan Kaufmann, 2017
Zahran, M; Heterogeneous computing: hardware and software perspectives., ACM Press, 2019

Teaching methods and learning activities

Lectures (1.5 hours) will explain the topics that make up the course syllabus, analysing realistic cases whenever possible. Laboratory practicals (1.5 hours) are used to introduce and discuss the projects and laboratory exercises, to give practical guidance on the project tools, and to follow the students' work outside the classroom sessions

Software

Xilinx Vivado

Evaluation Type

Distributed evaluation with final exam

Assessment Components

Designation	Weight (%)
Exame	60,00
Trabalho laboratorial	40,00
Total:	100,00

Amount of time allocated to each course unit

Designation	Time (hours)
Elaboração de projeto	42,00
Frequência das aulas	39,00
Estudo autónomo	81,00
Total:	162,00

Eligibility for exams

No constraints.

Calculation formula of final grade

Grading will include a distributed assessment component (lab work) and a final written exam with respective weights of 40% and 60%.
The distributed assessment is based on a set of laboratory tasks for groups of 2 students, presented and discussed in PL classes, but mainly performed outside class hours; the practical work focuses on the performance analysis of an application and its mapping to a reconfigurable SoC platform with high-level hardware synthesis tools.

Classification improvement

The classification of the final exam may be improved by doing an exam of similar complexity. The project grade cannot be improved.