VLSI Circuit Design

Code:

M.EEC054

Acronym:

PCVLSI

Keywords
Classification	Keyword
OFICIAL	Systems Electronics and Digital Systems

Instance: 2021/2022 - 2S

Active?	Yes
Responsible unit:	Department of Electrical and Computer Engineering
Course/CS Responsible:	Master in Electrical and Computer Engineering

Cycles of Study/Courses

Acronym	No. of Students	Study Plan	Curricular Years	Credits UCN	Credits ECTS	Contact hours	Total Time
M.EEC	18	Syllabus	1	-	6	39

Teaching language

English

Objectives

BACKGROUND

Very large scale integration (VLSI) of digital systems belong to the technological foundation of electronic and coputing systems  that enable the economic growth on which present day societies depend. VLSI circuits play a vital role in many areas of eletrical and computer engineering like telecommunications and information technology, with social profund social impact on many domains like health care, wnergy efficiency, and security.

OBJECTIVES

This course provides the students with basic knowledge about the technological and electrical aspects of digital CMOS integrated circuits and the corresponding design techniques, so that they are able to specify, design and implement CMOS ICs. The students will also acquire practical experience with ECAD design flows and tools for the development of complex ICs.

PERCENT DISTRIBUTION

• Scientific component: 60%
• Technological component: 40%

 

Learning outcomes and competences

After taking the course, the student will be able to:

1. Describe and explain the design flow for digital integrated circuit design [knowledge & understanding]
2. Identify and characterize the technological alternatives for implementing ASICs [knowledge & understanding]
3. Apply first-order MOS transistor model to digital circuit analysis and design [engineering analysis & design]
4. Analyse and design logic gates [engineering analysis & design]
5. Explain and apply interconnection models [engineering analysis & design]
6. Explain and apply the method of logical effort for gate sizing [knowledge & understanding, engineering analysis]
7. Explain and evaluate the electrical and temporal behaviour of the main CMOS logic families [engineering analysis]
8. Design logic cells, including layout design and post-layout simulation [engineering project]
9.  Use a commercial project flow to synthesize a digital ASIC [engineering project]

Competencies: VLSI systems design and validation, VLSI design process and tools, team work (all the design activities are done in groups); Time management (the larger projects requires careful management of the design process over time)

Working method

Presencial

Program

M1 Introduction to VLSI digital circuits: models, tasks and tools. Standard-cell and full-custom design flows.
M2 CMOS technology (manufacturing process and design rules). Modelling of small MOS transistors. Interconnection modelling.
M3. Combinational logic circuits: techniques for implementing static and dynamic circuits, including transmission gate circuits. Sizing of logical gates.
M4. Sequential circuits: latches, flip-flops; quality measures.
M5. Tools for full-custom design: simulation, layout editing, LVS, extraction.
M6. Implementation of application-specific ICs based on standard cells: floorplanning, placement and routing, clock signal distribution network synthesis, extraction and verification

Mandatory literature

Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic; Digital Integrated Circuits: A Design Perspective, Prentice-Hall, 2003. ISBN: 0-13-090996-3
Martins, E. F. V; Eletrónica Digital Integrada, Lidel, 2017
Sarkar, A., De. S., Chanda, M., & Sarkar, C. K; Low Power VLSI Design: Fundamentals, Walter de Gruyter, 2016

Complementary Bibliography

Neil Weste, David Harris; CMOS VLSI Design: A Circuits and Systems Perspective, 4ed, Addison-Wesley, 2010. ISBN: 0321547748

Teaching methods and learning activities

The lectures are used to present and discuss the fundamentals about a topic; relevant aspects related to the proposed work projects are discussed. The laboratory sessions are used for practising the design of digital CMOS circuits, as well as for practical evaluation exercises. Students also undertake one project assignments (in groups of two, almost entirely
out of class), the  full-custom design of a logic module.

Software

Cadene Innovus
Cadence Genus
Cadence IC Station (Layout design, physical synthesis)
HSpice

keywords

Technological sciences > Engineering > Electronic engineering
Technological sciences > Technology > Micro-technology > Microsystems
Technological sciences > Technology > Micro-technology > Subsystem modules

Evaluation Type

Distributed evaluation with final exam

Assessment Components

Designation	Weight (%)
Exame	30,00
Trabalho prático ou de projeto	70,00
Total:	100,00

Amount of time allocated to each course unit

Designation	Time (hours)
Elaboração de projeto	40,00
Estudo autónomo	83,00
Frequência das aulas	39,00
Total:	162,00

Eligibility for exams

No constraints.

Calculation formula of final grade

Student assessment has two components:

• one design project  (T)
• final exam (E)

Any missed components count as zero.

The final grade is calculated as follows: NFinal = 0.7×T + 0.3×E

To successfully complete the course unit, it is necessary to have E >= 6.0.

Final exam: open-book, 2:00H.

Classification improvement

The classification of the final exam may be improved by doing an exam of similar complexity. The project grade cannot be improved.