Digital Systems Design

Code:

EEC0055

Acronym:

PSDI

Keywords
Classification	Keyword
OFICIAL	Electronics and Digital Systems

Instance: 2020/2021 - 1S

Active?	Yes
Responsible unit:	Department of Electrical and Computer Engineering
Course/CS Responsible:	Master in Electrical and Computers Engineering

Cycles of Study/Courses

Acronym	No. of Students	Study Plan	Curricular Years	Credits UCN	Credits ECTS	Contact hours	Total Time
MIEEC	47	Syllabus	4	-	6	56	162
MI:EF	0	study plan from 2017/18	4	-	6	56	162

Teaching language

Portuguese

Objectives

This course aims to endow students with technological knowledge and design methodologies to build complex custom digital systems, targeting microelectronic technologies (application specific integrated circuits - ASIC and reconfigurable digital systems - FPGA). The activity developed in the course is focused on building abstract models of digital systems using industrial hardware description languages (Verilog HDL), perform model verification by logic simulation and synthesise from RTL descriptions, exploiting a strong laboratory activity around practical projects targeting FPGA platforms.

Learning outcomes and competences

After successfully completing this course the students should be able to:

- Identify and characterize the main design tasks in the digital design flow for microelectronic technologies (ASICs and FPGAs)

- Mastering the process of coding digital systems using hardware description languages (Verilog HDL), under the perspectives of design verification and automatic RTL synthesis.

- Planning the design verification process based on logic simulation tools and basic verification platforms.

- Design synchronous digital systems with one or more clock domains and understand the timing constraints associated with their implementation, including the problems associated to the generation, distribution and synchronization of clock signals.

- Evaluate and compare different logic implementations of basic arithmetic circuits, with respect to area and timing specifications.

- Apply design processes and methodologies to integrate pre-built blocks (intellectual property or IP), with practical application in a digital design environment for FPGAs.

- Identify the basic processes associated with the power consumption in digital microelectronic circuits (CMOS) and apply elementary design techniques to reduce the power consumption.

- Develop personal, professional and interpersonal skills (teamwork and oral and written communication) with the realization of group laboratory assignments and reports.

Working method

Presencial

Pre-requirements (prior knowledge) and co-requirements (common knowledge)

Elementary background on digital sistems and Boolean algebra

Program

Structured design flow of digital systems: design methodologies and models of representation of digital systems at different levels of abstraction; hierarchy and modularity. Hardware Description Languages (HDLs) for modelling, verification and logic synthesis. Design verification with logic simulation; functional and timing verification; elaboration of testbenches. Synthesis of digital systems at the Register Transfer Level (RTL); synthesis constraints (area and timing). Design of synchronous digital systems; issues related with the generation, management and distribution of clock signals; designs with multiple clock domains. Reconfigurable digital technologies: FPGAs and combined systems FPGA/microprocessor. Design of dedicated arithmetic datapaths: architectures of elementary arithmetic operators. Principles of low power digital design (logic, RTL and architectural levels).

Mandatory literature

Smith, Douglas J.; HDL chip design. ISBN: 0-9651934-3-8
Ciletti, Michael D.; Advanced digital design with the verilog HDL. ISBN: 0-13-089161-4

Complementary Bibliography

Bergeron, Janick; Writing testbenches. ISBN: 0-7923-7766-4
Palnitkar, Samir; Verilog HDL. ISBN: 0-13-451675-3

Teaching methods and learning activities

Theoretical classes (2 hours) will be based on the presentation of the themes of the course. Practical classes (2 hours) will be based on practical assignments to apply design methodologies, tools and concepts presented in theoretical classes. Practical assignments will be based on the use of XILINX design tools, using top-down design methodologies, based on Verilog hardware description language, automatic synthesis and implementation of reconfigurable systems based on FPGA devices. All support material will be available on line.

Software

QuestaSim 10.4
Xilinx ISE 14.6

keywords

Physical sciences > Computer science > Digital systems
Technological sciences > Engineering > Computer engineering

Evaluation Type

Distributed evaluation with final exam

Assessment Components

Designation	Weight (%)
Exame	50,00
Participação presencial	0,00
Trabalho laboratorial	50,00
Total:	100,00

Amount of time allocated to each course unit

Designation	Time (hours)
Estudo autónomo	50,00
Frequência das aulas	56,00
Trabalho laboratorial	56,00
Total:	162,00

Eligibility for exams

Students have to reach a minimum mark of 40% in the practical component of the course (laboratory assignments) to be admitted to the final exam. Also, students have to follow the rules established in the General Evaluation Rules of FEUP.

Calculation formula of final grade

The final grade FG will be computed by the following formula (the final exam 50% and the  laboratory assignments will have the same wheight):
FG= 0,1*LA1 + 0,05*LA2 + 0,35*LA3 + 0,5*FE  where:
LAi: Lab Assignment #i, i=1..3;
FE: Final Exam
To obtain approval the students should obtain a minimum mark of 10 out of 20 and they have to reach a minimum mark of 40% in the final exam and a minimum of 40% in the 3 laboratory assignments.

Examinations or Special Assignments

Special assignments which are done outside the regular season of assessment will be based on an exam and a practical assignment. Students with a special status, who reached a minimum mark of 40% in the practical component of the course in the previous year, do not need to do it again.

Internship work/project

None.

Special assessment (TE, DA, ...)

Students with a special status exempt of attending the practical classes, will have to do a complementary laboratory work, which is worth the same as the regular practical assignments (10 out 20).

Classification improvement

Students can improve their marks separately (exam and practical assignments). The improvement of the pratical assignments can be done in the next year.

Observations

Classes will be given in Portuguese. However, if there are foreign students who do not understand Portuguese, special classes will be organized in English for them.

The students already enrolled in the course in the previous academic year (2018/2019) can use their classification of the laboratory works obtained inthe previous year and take only the final exam in the current year.