Hardware/Software System Development

Code:

PDEEC0060

Acronym:

HSSD

Keywords
Classification	Keyword
OFICIAL	Electrical and Computer Engineering

Instance: 2018/2019 - 2S

Active?	Yes
Responsible unit:	Department of Electrical and Computer Engineering
Course/CS Responsible:	Doctoral Program in Electrical and Computer Engineering

Cycles of Study/Courses

Acronym	No. of Students	Study Plan	Curricular Years	Credits UCN	Credits ECTS	Contact hours	Total Time
PDEEC	3	Syllabus	1	-	7,5	70	202,5

Teaching language

English

Objectives

Learn the processes, methodologies, techniques and best practices associated to the development of digital integrated systems, combining software components running in one or more conventional CPUs with custom designed hardware blocks for accelerating the critical parts of an application.

Acquire the capability to analyze and evaluate the performance of a real-life computing application and to conceive and develop a hardware/software system capable of improving its performance, while running on a conventional computing system.

Learning outcomes and competences

After this course the students should be able to:
1. analyse and evaluate the potential increase in performance of a computing application, using heterogeneous application specific computing cores;
2. conceive and develop custom computing cores by applying high-level synthesis based digital design methodologies;
3. exploit conveniently the optimizations performed by high-level synthesis tools;
4. develop and apply high-level design verification processes to combined hardware/software systems
5. explore efficiently the hardware/software solution space for a real application, targeting a reconfigurable digital technology (FPGA)

Working method

Presencial

Pre-requirements (prior knowledge) and co-requirements (common knowledge)

Practice with digital design using hardware description languages (Verilog/VHDL) and RTL synthesis;
Practice with the design methodologies and tools for digital reconfigurable systems (FPGA).

Program

Heterogeneous multi-core system design:
1. Systems-on-Chip (SoC) and reconfigurable platforms
2. General purpose and application-specific cores
3. Customizable embedded processors
4. Performance-driven partitioning
5. Interprocessor communication infrastructures
6. Industrial design flows: methodologies and tools

System level modelling, verification and synthesis:
1. Electronic system level (ESL) design methodologies
2. Unified hardware/software verification
3. High-level synthesis of digital systems
4. Micro-architecture design

Mapping Techniques for Hardware/Software Systems:
1. From Software to Application-Specific Architectures;
2. Hardware/Software Partitioning;
3. Compiler Optimizations and Loop Transformations
4. Design Space Exploration Techniques

Mandatory literature

Philippe Coussy, Adam Morawiec; High-Level Synthesis From Algorithm to Digital Circuit: From Algorithm to Digital Circuit, Springer Science + Business Media B.V, 2008. ISBN: 1402085877
Michael Fingeroff; High-Level Synthesis Blue Book, Mentor Graphics Corporation, 2010. ISBN: 1450097243

Complementary Bibliography

João M. P. Cardoso, and Pedro C. Diniz; Compilation Techniques for Reconfigurable Architectures, Springer, 2008. ISBN: 0387096701

Comments from the literature

Besides the referred books, additional study materials are the reference manuals of the synthesis and design tools and a set of selected scientific papers to support the development of the individual work.

 

Teaching methods and learning activities

The course is organised in weekly classes with the students, with 3h duration. These sessions include lectures, presentations by the students about themes developed during the study and analysis of a scientific paper and presentation and discussion of the practical projects.

The work developed by the students is divided into the analysis and discussion of a set of scientific papers (one per student) focused in selected course topics, and in the development and presentation of a project focused on designing a hardware/software system, which the custom hardware components will be designed using high-level synthesis.  This course organisation fosters the self study and the active involvement of the students while preparing presentations on selected subjects of the course programme.

The lectures address the remaining course topics and are adjusted, either in the contents and deepness, to the background of the students in this domain.

Software

XILINX SDSoc ( embedded C/C++/OpenCL application development)
XILINX Vivado HLS (high-level synthesis)

keywords

Technological sciences > Technology > Computer technology > Systems technology
Technological sciences > Engineering > Computer engineering

Evaluation Type

Distributed evaluation without final exam

Assessment Components

Designation	Weight (%)
Defesa pública de dissertação, de relatório de projeto ou estágio, ou de tese	20,00
Participação presencial	0,00
Trabalho escrito	40,00
Trabalho laboratorial	40,00
Total:	100,00

Amount of time allocated to each course unit

Designation	Time (hours)
Elaboração de projeto	60,00
Estudo autónomo	74,00
Frequência das aulas	42,00
Trabalho de investigação	27,00
Total:	203,00

Eligibility for exams

The students should attend a minimum of 75% of the classes and perform the laboratory assignments.

Calculation formula of final grade

Assessment components:
P = analysis and presentation of a paper
L = laboratory project
I = individual assessment
Final grade = 0.4 P + 0.4 L + 0.2 I