VLSI Circuit Design

Code:

EEC0056

Acronym:

PCVL

Keywords
Classification	Keyword
OFICIAL	Electronics and Digital Systems

Instance: 2018/2019 - 2S

Active?	Yes
Web Page:	https://paginas.fe.up.pt/~jcf/ensino/disciplinas/mieec/pcvlsi/2018-19/index.html
Responsible unit:	Department of Electrical and Computer Engineering
Course/CS Responsible:	Master in Electrical and Computers Engineering

Cycles of Study/Courses

Acronym	No. of Students	Study Plan	Curricular Years	Credits UCN	Credits ECTS	Contact hours	Total Time
MIEEC	41	Syllabus	4	-	6	56	162

Teaching language

English

Objectives

BACKGROUND

Very large scale integration (VLSI) of digital systems belong to the technological foundation of electronic and coputing systems  that enable the economic growth on which present day societies depend. VLSI circuits play a vital role in many areas of eletrical and computer engineering like telecommunications and information technology, with social profund social impact on many domains like health care, wnergy efficiency, and security.

OBJECTIVES

This course provides the students with basic knowledge about the technological and electrical aspects of digital CMOS integrated circuits and the corresponding design techniques, so that they are able to specify, design and implement CMOS ICs. The students will also acquire practical experience with ECAD design flows and tools for the development of complex ICs.

PERCENT DISTRIBUTION

• Scientific component: 60%
• Technological component: 40%

 

Learning outcomes and competences

After taking the course, the student will be able to:

1. describe and explain the standard-cell design flow for digital ICs (from HDL description until post-layout validation) [knowledge & understanding];
2. identify and characterize the main technological options for ASIC/SOC implementation [knowledge & understanding];
3. apply the first-order model of MOSFET behavior to design and analysis of digital circuits [engineering analysis & design];
4. explain and apply interconnect models [knowledge & understanding, engineering analysis];
5. use SPICE simulator to analyze and design digital gates [engineering analysis & design];
6. explain and evaluate the electrical and temporal behavior of the main CMOS circuit families [engineering analysis];
7. design standard cells (includes electrical simulation, layout, and post-layout simulation) [engineering design];
8. use a commercial design flow to synthesize a standard-cell circuit starting from a Verilog description [engineering design];
9. explain and apply the method of "Logical effort" for gate sizing [knowledge & understanding, engineering analysis, engineering design];

Competencies: VLSI systems design and validation, VLSI design prrocess and tools, team work (all the design activities are done in groups); Time management (the larger projects requires careful management of the design process over time)

Working method

Presencial

Pre-requirements (prior knowledge) and co-requirements (common knowledge)

EEC0014: MOSFET operation.

EEC0006: digital logic gates; combinational and sequential circuits.

Program

The course comprises the following topics:

1. IC design flow: models, tasks and tools. Full-custom and standard cell design flows.
2. Basic aspects of CMOS technology, electrical and logical circuit behaviour. Modelling of sub-micrometer devices. Interconnect modelling.
3. Combinational and sequential logic: advanced static and dynamic implementation techniques.
4. Basic principles of low-power digital circuit design.
5. Design tools for full-custom design tasks: simulation and layout (HSPICE, Virtuoso Layout Editor).
6. Design and implementation of standard-cell based ASICs. Physical design aspects: floor planning, placement and routing. Simulation and verification. Clock signal distribution.
7. Industry-grade support tools for the design of very complex standard-cell-based ICs.

 

Mandatory literature

Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic; Digital Integrated Circuits: A Design Perspective, Prentice-Hall, 2003. ISBN: 0-13-090996-3

Complementary Bibliography

Neil Weste, David Harris; CMOS VLSI Design: A Circuits and Systems Perspective, 4ed, Addison-Wesley, 2010. ISBN: 0321547748
Erik Brunvand; Digital VLSI Chip Design with Cadence and Synopsys CAD Tools, Addison-Wesley, 2009. ISBN: 0321547993
Michael J. S. Smith; Application-Specific Integrated Circuits, Addison-Wesley, 1997. ISBN: 0-201-50022-1

Teaching methods and learning activities

The most important topics are presented and discussed in the lectures.

Exercises and case studies occupy the practical sessions, which are also used to discuss the design project. In addition, practical exercises for evaluation are also done in the practical sessions.

Students (working in groups of two) are required to implement one design  project.

Software

Cadence Encounter
Cadence RTL Compiler
Cadence IC Station (Layout design, physical synthesis)
HSpice

keywords

Technological sciences > Technology > Micro-technology > Subsystem modules
Technological sciences > Engineering > Electronic engineering
Technological sciences > Technology > Micro-technology > Microsystems

Evaluation Type

Distributed evaluation with final exam

Assessment Components

Designation	Weight (%)
Exame	40,00
Teste	18,00
Trabalho prático ou de projeto	42,00
Total:	100,00

Amount of time allocated to each course unit

Designation	Time (hours)
Elaboração de projeto	40,00
Estudo autónomo	74,00
Frequência das aulas	48,00
Total:	162,00

Eligibility for exams

No constraints.

Calculation formula of final grade

Student assessment has three components:

• one project assignment (T)
• three practical excercises  (P1, P2, P3)
• final exam (E)

Any missed components count as zero.

The project and the three practical exercises compose the distributed evaluation.

The grade for the distributed evaluation (NDist) is given by: NDist = 0.7×T + 0.3×P

The final grade is calculated as follows: NFinal = 0.6×NDist + 0.4×E

In order to successfully complete the course unit, all the following conditions must be met:

• NDist >= 8.0
• E >= 6,0
• NFinal >= 10

Final exam: open-book, 2:30H.

Special assessment (TE, DA, ...)

Written exam (open-book, 3H) covering the complete subject matter.

Classification improvement

The classification of the final exam may be improved by doing an exam of similar complexity. The project grade cannot be improved.