Computer Architecture and Organization

Code:

EIC0083

Acronym:

AOCO

Keywords
Classification	Keyword
OFICIAL	Computer Arquitechture

Instance: 2009/2010 - 1S

Active?	Yes
Responsible unit:	Electronics and Digital Systems
Course/CS Responsible:	Master in Informatics and Computing Engineering

Cycles of Study/Courses

Acronym	No. of Students	Study Plan	Curricular Years	Credits UCN	Credits ECTS	Contact hours	Total Time
MIEIC	162	Syllabus since 2009/2010	1	-	6	56	162

Teaching language

Suitable for English-speaking students

Objectives

BACKGROUND

Computer hardware is the physical embodiment of the abstract computational models used in informatics. At each technology node, the hardware organization defines the bounds for efficient computation and determines the main performance characteristics of computer systems. Computer architecture also decisively influences the features and capabilities of programming languages.

SPECIFIC AIMS

This course introduces the principles of operation and general structure of a modern computer and its general structure, with particular emphasis on the contribution of each subsystem to the overall performance. The analysis of the implementation technology of computers (logic circuits and memory), together with the basic principles of digital information representation, will allow students to identify and describe the principles of computer operation, programming languages and software development.


PREVIOUS KNOWLEDGE

Since this is an entry course, no previous knowledge from other course units is required.

PERCENT DISTRIBUTION

Scientific component: 70%
Technological component: 30%

LEARNING OUTCOMES
(Programme outcomes: K&U: knowledge & understanding; EA: engineering analysis; ED: engineering design)

After completing this course, students will be able to:

- Identify and describe the major subsystems of a personal computer: processing unit, memory and peripherals [K&U];
- Explain and evaluate the performance of computers in simple scenarios involving the fundamental performance equation and Amdahl's law [K&U, EA];
- Describe and interpret basic forms of digital representation of numerical information [K&U];
- Explain and perform basic binary arithmetic operations [K&U];
- Identify and explain the operation of basic logic circuits [K&U];
- Distinguish combinational and sequential circuits [K&U];
- Determine the logic diagrams corresponding to a Boolean expression and vice-versa [K&U];
- Explain the operation of basic logic circuits like comparators and adders, and establish the corresponding Boolean expressions [K&U];
- Examine the operation of a Moore state machine [K&U];
- Design state machines for simple control systems [ED];
- Classify and categorize the types of instructions of a processing unit [K&U];
- Explain the basic principles of instruction encoding and identify its impact on performance [K&U; EA];
- Write simple programs in assembly language involving Boolean and arithmetic operations, tests and jumps [K&U; ED];
- Describe the operation of a single-cycle processing unit [K&U];
- Specify simple extensions of the single-cycle processing unit [K&U; ED];
- Describe and explain instruction pipelines and their impact on performance [EA];
- Describe the operation of a pipelined processing unit [K&U];
- Apply state machines to the analysis of the control unit of a pipeline [ED];
- Identify data and control conflicts that may occur in a pipelined instruction unit [K&U];
- Assess the impact of pipeline conflicts on performance for simple scenarios [EA];
- Distinguish between static and dynamic memories, and identify their applications [K&U];
- Explain the working principle of the two types of memories [K&U];
- Identify the different levels of the memory hierarchy of a personal computer [K&U];
- Explain the operation principle of cache memories [K&U];
- Describe the organization of a cache memory (associativity) and the handling of cache misses; treatment of access failures [K&U];
- Evaluate numerically the influence of the memory hierarchy on performance (for simple scenarios) [ED];
- Explain the problems associated with the use of cache memory in multiprocessors [K&U].

Program

1. Introduction. Computers: application areas of and their characteristics. Programming: high-level languages, low-level languages. Conceptual model of program execution.

2. Components of a computer: CPU (datapath and control unit), memory, input/output peripherals. Technological evolution of processors and memories.

3. Understanding the performance of CPUs. The basic performance equation. Benchmarks (SPEC). Power consumption. Amdahl's Law.

4. Representation of information: the binary representation of integers (with and without sign). Base 8 and 16. Basic arithmetic (addition, subtraction, multiplication, division). ASCII code and Unicode. IEEE-754 floating-point format.

5. Combinational logic circuits. Boolean expressions. Elementary logic gates. Logic diagrams. Logic circuits: comparator, multiplexer, adder/subtractor.

6. Synchronous circuits. Memory elements. Moore-type state machines. Controllers based on state machines.

7. Instruction set of a processor. Types of instructions: arithmetic, logical, comparison and jump. Address modes. Instruction encoding. Synchronization instructions.

8. Basic concepts of assembly programming. Assembler.

9. Organization of a processing unit. Single-cycle CPU. Pipelining. Organization of a pipelined datapath. Pipeline control. Pipeline hazards: data and control conflicts. Strategies for handling conflicts. Impact of conflicts on performance.

10. Static and dynamic memories: organization and conceptual model. Memory hierarchies.

11. Cache mempries. Principles of operation, internal organization, associativity, handling of cache misses. Performance of a CPU with cache. Reduction of the penalties associated with access misses. Basic aspects of the interaction between cache memories and multiple processing units.

Mandatory literature

Patterson, David A.; Computer organization and design. ISBN: 978-0-12-374493-7

Teaching methods and learning activities

The course includes lectures on the subject matter, including, where appropriate, the presentation of examples and their discussion. The practical classes include the presentation, analysis and resolution of a number of problems, discussion of case studies, and short questionnaires.

keywords

Technological sciences > Engineering > Computer engineering

Evaluation Type

Distributed evaluation without final exam

Assessment Components

Description	Type	Time (hours)	Weight (%)	End date
Attendance (estimated)	Participação presencial	68,00
Test n. 1	Exame	18,00
Test n. 2	Exame	18,00
	Total:	-	0,00

Amount of time allocated to each course unit

Description	Type	Time (hours)	End date
Study	Estudo autónomo	58
	Total:	58,00

Eligibility for exams

The "frequência" grade is based on the results of four questionnaires on the subject matter. The questionnaires are taken in the practical classes. Each questionnaire takes 15 minutes (closed book).

The mark for this component (NFreq) is the arithmetic mean of the three best marks on the questionnaires (all questionnaires have the same weight).

In order to be eligible for completion of the course, the student must have NFreq> = 7.5.

A no-show counts as a zero mark.

Calculation formula of final grade

For students having NFreq >= 7.5, the final course grade is determined by that NFreq and the marks for two tests (T1 and T2). Each test (closed book) takes 60 minutes. Both tests have the same weight. A no-show counts as zero.

The combines test grade is: T = 0.5 x T1 + 0.5 x T2

The final grade for the course (NFinal) is given by:
NFinal = 0, T + 7 x 0.3 x NFreq

To complete the course, the students must have:
NFinal >= 10 AND T >= 7.5.

Examinations or Special Assignments

Students having missed an evaluation for valid reasons, may attend a replacement test at a different date (set by the course instructors).

Special assessment (TE, DA, ...)

Students not required to attend the practical classes must attend the tests. In this case, the final grade is given by the arithmetic mean of the test grades:
NFinal = T.

Classification improvement

As this is a course with distributed evaluation only, grades may be improved by attending the course in the following year.

Observations

If necessary, the course will be given in English.