VLSI Circuit Design

Code:

EEC0056

Acronym:

PCVL

Keywords
Classification	Keyword
OFICIAL	Electronics and Digital Systems

Instance: 2012/2013 - 2S

Active?	Yes
Web Page:	http://paginas.fe.up.pt/~jcf/ensino/disciplinas/mieec/pcvlsi/2012-13/index.html
Responsible unit:	Department of Electrical and Computer Engineering
Course/CS Responsible:	Master in Electrical and Computers Engineering

Cycles of Study/Courses

Acronym	No. of Students	Study Plan	Curricular Years	Credits UCN	Credits ECTS	Contact hours	Total Time
MIEEC	13	Syllabus (Transition) since 2010/2011	4	-	6	63	162
		Syllabus	4	-	6	63	162

Teaching language

Suitable for English-speaking students

Objectives

BACKGROUND

Very large scale integration (VLSI) of digital systems belong to the technological foundation that enables economic growth on which present day societies depend. VLSI circuits play a vital role in areas like telecommunications, information technology, health care, security, and many others.

OBJECTIVES

This course provides the students with basic knowledge about the technological aspects of digital CMOS integrated circuits and the corresponding design techniques, so that they are able to specify, design and implement CMOS ICs. The students will also acquire practical experience with ECAD design flows and tools for the development of complex ICs.

PERCENT DISTRIBUTION

• Scientific component: 60%
• Technological component: 40%

Learning outcomes and competences

After taking the course, the student will be able to:

1. describe and explain the standard-cell design flow for digital ICs (from HDL description until post-layout validation) [knowledge & understanding];
2. identify and characterize the main technological options for ASIC/SOC implementation [knowledge & understanding];
3. apply the first-order model of MOSFET behavior to design and analysis of digital circuits [engineering analysis & design];
4. explain and apply interconnect models [knowledge & understanding, engineering analysis];
5. use SPICE simulator to analyze and design digital gates [engineering analysis & design];
6. explain and evaluate the electrical and temporal behavior of the main CMOS circuit families [engineering analysis];
7. design standard cells (includes electrical simulation, layout, and post-layout simulation) [engineering design];
8. specify a circuit in Verilog [engineering design];
9. use a commercial design flow to synthesize a standard-cell circuit starting from a Verilog description [engineering design];
10. explain and apply the method of "Logical effort" for gate sizing [knowledge & understanding, engineering analysis, engineering design];
11. identify and explain the basic principles of low-power digital circuits [knowledge & understanding].

Transferable skills: All the design activities are done in groups. The larger projects require careful management of the design process.

Working method

Presencial

Pre-requirements (prior knowledge) and co-requirements (common knowledge)

EEC0028: MOSFET operation.

EEC0006: digital gates.

Program

1. IC design flow: models, tasks and tools. Full-custom and standard cell design flows.


2. Basic aspects of CMOS technology, electrical and logical circuit behaviour. Modeling of submicrometer devices. Interconnect modeling.


3. Combinational and sequential logic: advanced static and dynamic implementation techniques.


4. Principles of low-power digital circuit design.


5. Design of memory blocks and other regular structures. 


6. Design tools for full-custom design tasks: simulation and layout (HSPICE, Virtuoso Layout Editor).


7. Design and implementation of standard-cell based ASICs. Physical design aspects: floorplanning, placement and routing. Simulation and verification. Clock signal distribution.


8. Industry-grade support tools for the design of very complex stadrad-cell-based ICs.

Mandatory literature

Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic; Digital Integrated Circuits: A Design Perspective, Prentice-Hall, 2003. ISBN: 0-13-090996-3

Complementary Bibliography

Neil Weste, David Harris; CMOS VLSI Design: A Circuits and Systems Perspective, 4ed, Addison-Wesley, 2010. ISBN: 0321547748
Erik Brunvand; Digital VLSI Chip Design with Cadence and Synopsys CAD Tools, Addison-Wesley, 2009. ISBN: 0321547993
Michael J. S. Smith; Application-Specific Integrated Circuits, Addison-Wesley, 1997. ISBN: 0-201-50022-1

Teaching methods and learning activities

The most important topics are presented and discussed in the lectures.

Exercises and case studies occupy the practical sessions, which are also used to discuss the design project. In addition, practical exercises for evaluation are also done in the practical sessions.

Students (working in groups of two) are required to implement one circuit design  project.

Software

Cadence Encounter
Cadence IC Station (Layout design, physical synthesis)
Synopsys Design Compiler

keywords

Technological sciences > Engineering > Electronic engineering
Technological sciences > Technology > Micro-technology > Subsystem modules
Technological sciences > Technology > Micro-technology > Microsystems

Evaluation Type

Distributed evaluation with final exam

Assessment Components

Description	Type	Time (hours)	Weight (%)	End date
Attendance (estimated)	Participação presencial	68,00
Practical exercise 1	Teste	2,00	8,30
Practical exercise 2	Teste	2,00	8,30
Practical exercise 3	Teste	2,00	8,40
Exam	Exame	3,00	50,00
Circuit design project	Trabalho escrito	40,00	25,00
	Total:	-	100,00

Amount of time allocated to each course unit

Description	Type	Time (hours)	End date
Autonomous study	Estudo autónomo	45
	Total:	45,00

Eligibility for exams

The students cannot miss more than 25% of the course sessions.

Calculation formula of final grade

Student assessment has three components:

 

• one project assignment (T)
• three practical excercises  (P1, P2, P3)
• final exam (E)

Any missed components count as zero.

The project and the three practical exercises compose the distributed evaluation.

The grade for the distributed evaluation (NDist) is given by:

NDist = 0.5 x T + 0.5 x (P1+P2+P3)/3

The final grade is calculated as follows:

NFinal = 0.6 x NDist + 0.4 x E

where E is the grade of the final exam.

In order to successfully complete the course unit, all the following conditions must be met:

• NDist >= 8.0
• E >= 7.5
• NFinal >= 10

Final exam: open-book, 2:30H.

Special assessment (TE, DA, ...)

Written exam (open-book, 3H).

Classification improvement

Grade improvement for complete course: special exam (open-book, 3H). The classification of the final exam may be improved by doing an exam of similar complexity (open-book, 2:30H).