VLSI Circuit Design

Code:

EEC0056

Acronym:

PCVL

Keywords
Classification	Keyword
OFICIAL	Electronics and Digital Systems

Instance: 2007/2008 - 2S

Active?	Yes
Web Page:	http://paginas.fe.up.pt/~jcf/ensino/disciplinas/mieec/pcvlsi/2007-08b/index.html
Responsible unit:	Electronics and Digital Systems
Course/CS Responsible:	Master in Electrical and Computers Engineering

Cycles of Study/Courses

Acronym	No. of Students	Study Plan	Curricular Years	Credits UCN	Credits ECTS	Contact hours	Total Time
MIEEC	24	Syllabus since 2006/2007	4	-	6	-
		Syllabus since 2007/2008	4	-	6	-
		Plano para alunos que em 2006 estiveram no 3º ano	4	-	6	-
		Plano para alunos que em 2006 estiveram no 5º ano	5	-	6	-
		Plano para alunos que em 2006 estiveram no 4º ano	5	-	6	-

Teaching language

Portuguese

Objectives

The main aim is to provide the students with basic knowledge about the technological aspects of digital CMOS integrated circuits and the corresponding design techniques, so that they are able to specify, design and implement CMOS ICs. The students will also acquire practical experience with EECAD design flow and tools for the design of complex ICs.

Program

IC design flow: models, tasks and tools. Full-custom and standard cell design flows.

Review of basic aspects of CMOS technology, electrical and logical circuit behaviour. Modeling of submicrometer devices.

Combinational and sequential logic: advanced static and dynamic implementation techniques. Design of digital blocks for complex ICs: arithmetic circuits, memory, PLAs and other regular structures.

Design and implementation of standard-cell based ASICs. Basic principles of digital systems specification using hardware description languages. Introduction to Verilog. High-level sysnthesis of digital systems. Technology mapping. Physical design aspects: floorplanning, placement and routing. Simulation and verification.

Global performance-related aspects: global signals, clock trees, power consumption. Basic aspects of low-power digital circuit design.

Industry-grade support tools for very complex ICs: Cadence IC Station and Synopsys Design Compiler.

Mandatory literature

Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic; Digital Integrated Circuits: A Design Perspective, Prentice-Hall, 2003. ISBN: 0-13-090996-3

Complementary Bibliography

Michael J. S. Smith; Application-Specific Integrated Circuits, Addison-Wesley, 1997. ISBN: 0-201-50022-1
Kang, Sung-Mo (Steve); CMOS digital integrated circuits. ISBN: 0-0711-6427-8 )

Teaching methods and learning activities

Students (working in group) are required to implement two small projects.

The most important topics are presented in the lectures. Exercises and case studies are performed in the practical sessions.

Software

Cadence Virtuoso
Cadence SOC Encounter
Synopsys Design Compiler

Evaluation Type

Distributed evaluation with final exam

Assessment Components

Description	Type	Time (hours)	Weight (%)	End date
Subject Classes	Participação presencial	56,00
Preparation for final exam	Exame	20,00
ASIC design	Trabalho escrito	28,00
Full-custom CMOS circuit design	Trabalho escrito	28,00
	Total:	-	0,00

Amount of time allocated to each course unit

Description	Type	Time (hours)	End date
Self-study	Estudo autónomo	30
	Total:	30,00

Eligibility for exams

The Frequency note (Freq) is calculated as follows:

Freq = 0.3 x TP1 + 0.7 x TP2

TP1: project assignment n. 1
TP2: projectl assignment n. 2

In order to complete the course, the student must have Freq >= 8.0.

Calculation formula of final grade

The final classification (NFinal) is calculated as follows:

NFinal = 0.4 x Freq + 0.6 x E

E: final exam classification

Final exam: open-book, 2H.

Classification improvement

Whole course: special exam (open-book, 3H).

The classification of the final exam may be improved by doing an exam of similar complexity.

NFreq cannot be improved individually.