Digital Systems Design

Code:

EEC0055

Acronym:

PSDI

Keywords
Classification	Keyword
OFICIAL	Electronics and Digital Systems

Instance: 2006/2007 - 2S

Active?	Yes
Web Page:	http://www.fe.up.pt/~aja/PSDI_200607-2S
Responsible unit:	Electronics and Digital Systems
Course/CS Responsible:	Master in Electrical and Computers Engineering

Cycles of Study/Courses

Acronym	No. of Students	Study Plan	Curricular Years	Credits UCN	Credits ECTS	Contact hours	Total Time
LEEC	1	Plano de estudos de transição para 2006/07	4	6	6	63	160

Teaching language

Portuguese

Objectives

This course will give the students the basic theoretic and practical skills for designing complex digital systems, targeted to microelectronic devices, either application specific integrated circuits (ASIC) or digital programmable devices (FPGA). The course provides a strong hands-on experience, where the students exploit industrial EDA tools for designing and implementing small projects.

Program

Structured Digital Design; Typical top-down and bottom-up design flow: models and design automation tools; Hardware description languages: logic, RTL and behavioral modeling with Verilog HDL for synthesis and simulation (testbenches); Design verification at different abstraction levels: functional and logic validation and timing verification; Design of testbenches for functional verification; FPGA-based prototyping; RTL/logic synthesis (with XILINX XST); Design of complex synchronous digital systems: control-path vs. datapath, timing limitations, clock distribution, pipelining, retiming; Architecture of custom arithmetic operators for fixed-point and floating point number formats; Principles of low-power digital design at the device, logic, RTL and system levels.

Mandatory literature

Ciletti, Michael D.; Advanced digital design with the verilog HDL. ISBN: 0-13-089161-4
Smith, Douglas J.; HDL chip design. ISBN: 0-9651934-3-8

Complementary Bibliography

Bergeron, Janick; Writing testbenches. ISBN: 0-7923-7766-4
Palnitkar, Samir; Verilog HDL. ISBN: 0-13-451675-3

Teaching methods and learning activities

Lectures supported by slide presentations in one 2-hour block; the other 2-hour block consist in a practical class, that will be used mainly to present the projects and tools to be used and to discuss the stage of student's work. The practical classes will be used for the development of 3 projects following the top-down design flow based on Verilog HDL modelling, RTL synthesis and implementation on a FPGA based prototyping board. The Xilinx ISE 8.2 framework will be used.

Software

Modelsim XE 6
Xilinx ISE 8.2

Evaluation Type

Distributed evaluation without final exam

Assessment Components

Description	Type	Time (hours)	Weight (%)	End date
Subject Classes	Participação presencial	56,00
Mini-exam 1	Exame	1,00		2007-04-11
Mini-exam 2	Exame	1,00		2007-05-30
Laboratorial Work 1	Trabalho escrito	4,00		2007-03-12
Laboratorial Work 2	Trabalho escrito	6,00		2007-04-02
Laboratorial Work 3	Trabalho escrito	15,00		2007-05-28
	Total:	-	0,00

Amount of time allocated to each course unit

Description	Type	Time (hours)	End date
Study of the matters exposed in the theoretical classes	Estudo autónomo	35
Familiarization with design tools	Estudo autónomo	12
Study and preparation of practical works	Estudo autónomo	30
	Total:	77,00

Eligibility for exams

Besides the condition stated int the general evaluation rules, to attain frequency a student must obtain at least 4 points in the practical evaluation component (in a total of 11 points).

Calculation formula of final grade

To obtain approval, a student must attain a final classification (FC) of 10 points calculated with the following expression:

FC= 0.1*PW1 + 0.15*PW2 + 0.3*PW3 + 0.2*ME1 + 0.25*ME2

PWi: classification of practical work i
MEi: classification of mini-exam i

Examinations or Special Assignments

The students with special evaluation requirements, will be submitted to special examinations that include the same theoretical and practical components considered in the normal evaluation.

Special assessment (TE, DA, ...)

The students that will not attend the practical classes will be submitted to a special practical evaluation that will account with 11 points to the final classification.

Classification improvement

The classification improvement can be obtained in the next year, and may be done separately for the theoretical and practical evaluation components.