Digital Systems Design
Keywords |
Classification |
Keyword |
OFICIAL |
Electronics and Digital Systems |
Instance: 2007/2008 - 1S
Cycles of Study/Courses
Teaching language
Portuguese
Objectives
This course will give the students the basic theoretic and practical skills for designing complex digital systems, targeted to microelectronic devices, either application specific integrated circuits (ASIC) or digital programmable devices (FPGA). The course provides a strong hands-on experience, where the students exploit industrial EDA tools for designing and implementing small but realistic projects of digital systems.
Program
Structured Digital Design; Typical top-down and bottom-up design flow: models and design automation tools; hierarchical design. Reconfigurable technologies for implementation of digital systems: FPGAs and embedded processor-FPGA systems. Hardware description languages: logic, RTL and behavioral modeling with Verilog HDL for synthesis and simulation (testbenches). Synthesis of digital systems: RTL/logic synthesis and behavioural systhesis; logic synthesis under timing constraints. Design verification at different abstraction levels: functional and logic validation and timing verification; design of testbenches for functional and post-layout verification. Design of synchronous digital systems: control-path vs. datapath; clocking issues; systems with multiple clock domains. Architecture of custom arithmetic operators for fixed-point and floating point number formats; Principles of low-power digital design at logic, RTL and system levels.
Mandatory literature
Smith, Douglas J.;
HDL chip design. ISBN: 0-9651934-3-8
Ciletti, Michael D.;
Advanced digital design with the verilog HDL. ISBN: 0-13-089161-4
Complementary Bibliography
Bergeron, Janick;
Writing testbenches. ISBN: 0-7923-7766-4
Palnitkar, Samir;
Verilog HDL. ISBN: 0-13-451675-3
Teaching methods and learning activities
Lectures supported by slide presentations in one 2-hour block; the other 2-hour block consist in a practical class, that will be used mainly to present the projects and tools to be used and to discuss the stage of student's work. The practical classes will be used for the development of 3 projects following the top-down design flow based on Verilog HDL, RTL synthesis and implementation on a FPGA based prototyping board. The Xilinx ISE 8.2 framework will be used.
Software
ModelSim XE
Xilinx System Generator
Xilinx ISE 8.2
Evaluation Type
Distributed evaluation without final exam
Assessment Components
Description |
Type |
Time (hours) |
Weight (%) |
End date |
Subject Classes |
Participação presencial |
56,00 |
|
|
Minitest 2 |
Exame |
1,00 |
|
2007-12-19 |
Minitest 1 |
Exame |
1,00 |
|
2007-10-31 |
Laboratory 3 |
Trabalho escrito |
40,00 |
|
2007-12-20 |
Laboratory 2 |
Trabalho escrito |
15,00 |
|
2007-11-08 |
Laboratory 1 |
Trabalho escrito |
7,00 |
|
2007-10-11 |
|
Total: |
- |
0,00 |
|
Amount of time allocated to each course unit
Description |
Type |
Time (hours) |
End date |
Study of course subjects |
Estudo autónomo |
30 |
|
Study of the design tools |
Estudo autónomo |
10 |
|
|
Total: |
40,00 |
|
Eligibility for exams
Besides the condition stated int the general evaluation rules, to attain frequency a student must obtain at least 5 points in the practical evaluation component (in a total of 12points).
Calculation formula of final grade
To obtain approval, a student must attain a final classification (FC) of 10 points calculated with the following expression:
FC= 0.1*PW1 + 0.1*PW2 + 0.4*PW3 + 0.2*ME1 + 0.2*ME2
where:
PWi: classification of practical work i (i=1..3)
MEi: classification of mini-exam i (i=1..2)
To pass a student must fulfil the following three conditions:
Obtain a final classification greater or equal to 10 points (50%)
Obtain a minimum classification of 6 points in the laboratory works (50%)
Obtain a minimum classification of 4 points in the sum of the two minitests (50%)
Examinations or Special Assignments
The students with special evaluation requirements, will be submitted to special examinations that include the same theoretical and practical components considered in the normal evaluation.
Special assessment (TE, DA, ...)
The students that will not attend the practical classes will be submitted to a special practical evaluation that will account with 12 points to the final classification.
Classification improvement
The classification improvement can be obtained in the next year, and may be done separately for the theoretical and practical evaluation components.
Observations
Teaching language will preferably be Portuguese. However, if the course is attended by foreign students who do not understand Portuguese, then the teaching language will be English.