Computer Architecture

Code:

L.EEC012

Acronym:

AC

Keywords
Classification	Keyword
OFICIAL	Systems Electronics and Digital Systems

Instance: 2023/2024 - 1S

Active?	Yes
Responsible unit:	Department of Electrical and Computer Engineering
Course/CS Responsible:	Bachelor in Electrical and Computer Engineering

Cycles of Study/Courses

Acronym	No. of Students	Study Plan	Curricular Years	Credits UCN	Credits ECTS	Contact hours	Total Time
L.EEC	272	Syllabus	2	-	6	52	162

Teaching language

Portuguese

Objectives

This course introduces the principles of operation of a modern computer and its overall architecture, with emphasis on the contribution of each subsystem to the overall performance.

The analysis of the physical implementation technology of computers (especially the organization of their CPU and memory hierarchy), as well as the instruction set architecture (ISA), will enable students to identify and describe fundamental principles of computer operation, programming languages ​​(assembly in particular), and software development.

Learning outcomes and competences

After completing this course, students should be able to:

• Identify and describe the major subsystems of a personal computer: processing unit, memory and peripherals;


• Explain and evaluate the performance of computers in simple scenarios involving the performance equation of and Amdahl's law;


• Classifying and characterizing the types of instructions in a processing unit;


• Explain the basic principle of encoding instructions and identify their impact on performance;


• Write simple programs in RISC-V assembly language involving arithmetic, boolean, comparison and jump operations;


• Describe the operation of a unicycle processing unit;


• Describe and explain the concept of "pipeline" and its impact on performance;


• Describe the operation of a pipelined processing unit;


• Apply knowledge of finite state machines to the analysis of the control unit of a pipelined processing unit;


• Identify data and control hazards that can arise in a pipelined processing unit;


• Calculate the impact of conflicts in the performance of a "pipeline" in simple scenarios;


• Distinguish between static and dynamic memories, and identify the respective areas of use;


• Explain the principle of operation of both types of memories;


• Identify the various levels of the memory hierarchy in a personal computer;


• Explain the working principle of "cache" memory;


• Describe the organization of a "cache" memory (associativity) and the handling of memory misses;


• Numerically evaluate the influence of memory hierarchy on performance.

Working method

Presencial

Pre-requirements (prior knowledge) and co-requirements (common knowledge)

Good knowledge in the field of Digital Systems as well as basics of Programming.

Program

The sylabus of Computer Architecture consists of the following topics:

• Introduction. Areas of application of computers and their characteristics. Programs: high-level languages, low-level languages. Conceptual model of program execution.


• Components of a computer: CPU (data path and control unit), memory, peripheral input/output. Evolution of processors and memories technology.


• Understanding the performance of CPUs. Performance equation. Benchmarks (SPEC). Energy consumption. Amdahl's Law.


• Instruction set of a RISC-V processor. Types of instructions: arithmetic, logical, comparison and jump. Addressing modes. Instruction coding.


• Basic concepts of programming in "assembly" language. Analysis and implementation of simple programs using a RISC-V architecture emulator (RARS).


• Organization of a processing unit. Unicycle organization of a CPU. Pipelining concept. Organization of a pipeline data path. Pipeline control. Pipeline conflicts: data and control hazards. Strategies for dealing with conflicts. Impact of conflict on performance.


• Static and Dynamic Memory: organization and conceptual model. Memory hierarchy.


• Cache Memory: principle of operation, internal organization, associativity and handling cache misses. CPU performance with cache memory. Reduction of penalties associated with access misses.

Mandatory literature

David A. Patterson & John L. Hennessy; Computer Organization and Design, The Hardware/Software Interface - RISC-V edition, Elsevier, 2nd edition, 2021. ISBN: 978-0-12-820331-6
António José Araújo, Hélio Sousa Mendonça; Slides, conjuntos de exercícios e outros documentos, 2023

Teaching methods and learning activities

In theoretical classes, subjects about computer architecture in general and the RISC-V architecture in particular will be exposed, accompanied by the resolution of exercises.

In practical laboratory classes, exercises involving the topics covered in theoretical classes will be solved. Additionally, simple RISC-V assembly programs will be developed and tested using a simulator (RARS), as well as support tools that detail the internal operation of the CPU and cache memory.

Software

RARS

Evaluation Type

Distributed evaluation with final exam

Assessment Components

Designation	Weight (%)
Exame	60,00
Teste	40,00
Total:	100,00

Amount of time allocated to each course unit

Designation	Time (hours)
Estudo autónomo	110,00
Frequência das aulas	52,00
Total:	162,00

Eligibility for exams

Obtaining attendance requires students to enroll in classes (to participate in PL classes) and not exceed the limit number of absences, corresponding to 25% of the foreseen PL classes, that is, they do not have more than 3 absences.

Enrolling in practical classes makes them lose the "Frequência" (attendance) they may have obtained in previous academic year.

Calculation formula of final grade

The final grade (CF) is calculated by:

CF = 0,4 x Q + 0,6 x E

where:

• Q = Quizzes taken in PL classes
• E = Final exam

Students who have obtained attendance in the previous academic year can obtain CF by taking the exam only (CF=E) or, alternatively, by using the assessment component carried out in PL classes (corresponding to Q) obtained in the previous year and taking the exam.
These students can also choose to enroll in classes as if they were first-time students, losing their previous attendance and being assessed as first-time students.

Students without "Frequência" (attendance) are not admitted to the exam.

The grade obtained in the appeal period exam, if higher, replaces the grade obtained in the exam (E).

Classification improvement

Classification improvement can be done by taking the "appeal" exam or taking the exam at the normal season of the following academic year.

Observations

Doubts regarding matters of the PL classes should be asked, preferably, to the teachers of the respective classes.

The teachers responsible for this curricular unit are available for appointment (via email) or at a time to be defined:

• Prof. António José Araújo (AJA), aja@fe.up.pt, gabinete I236;
  
  
• Prof. Hélio Sousa Mendonça (HSM), hsm@fe.up.pt, gabinete I230.