Computer Architecture

Code:

L.EIC006

Acronym:

AC

Keywords
Classification	Keyword
OFICIAL	Informatics Engineering and Computing

Instance: 2021/2022 - 2S

Active?	Yes
Responsible unit:	Department of Electrical and Computer Engineering
Course/CS Responsible:	Bachelor in Informatics and Computing Engineering

Cycles of Study/Courses

Acronym	No. of Students	Study Plan	Curricular Years	Credits UCN	Credits ECTS	Contact hours	Total Time
L.EIC	402	Syllabus	1	-	6	52	162

Teaching language

Portuguese

Objectives

BACKGROUND

The architecture of a computer reflects the current technological advancement, but also sets the limits of its capabilities and performance. Variants of the ARM instruction set are used in the vast majority of current mobile platforms (tablets, cell phones). Both the system architecture and the instruction set have a profound impact on the daily practice of computer engineers.engineers.

SPECIFIC AIMS

The curricular unit "Computer Architecture" aims to develop, combine and apply in an integrated way concepts from the areas of Computer Architecture and Programming Languages. Thus, the curricular unit explores the relationship between the instruction set and low-level programming (assembly language). Mechanisms to support efficient program execution, such as instruction pipelining and jump prediction, will also be addressed. Recognizing that computer architecture goes far beyond the CPU architecture, the curricular unit will also address memory, storage and peripheral subsystems. Upon successful completion of this curricular unit, the student will have acquired the ability to identify and describe the architecture of computing platforms currently in use, as well as the ability to apply assembly programming techniques in the implementation of algorithms.

PERCENT DISTRIBUTION

• Scientific component: 60%
• Technological component: 40%

Learning outcomes and competences

After successfully completing this curricular unit, the student should be able to:

1. Explain procedure call conventions and write C++/”assembly” programs.


2. Describe SIMD instructions and apply them in high-performance subroutines.


3. Explain basic instruction-level pipelining and its effect on performance.


4. Explain the mechanisms for handling data and control dependencies.


5. Describe cache memory organizations and explain their use to improve performance.


6. Evaluate the performance of single-core processors.


7. Describe the basic organization of a symmetric multiprocessor (with multiple cores and shared memory).


8. Explain the processor's interaction with input/output (I/O) devices.


9. Explain the use of interrupts.


10. Describe the characteristics of current secondary storage technologies and assess their impact on performance.


11. Describe the behaviour of superscalar architectures (simultaneous issue of instructions; out-of-order execution).

Working method

Presencial

Pre-requirements (prior knowledge) and co-requirements (common knowledge)

Prerequisite:

- Fundamentals of computer systems (L.EIC004): principles of assembly language programming (ARM) and computer organization.

Co-requirement:

- Programming (L.EIC009): basic principles of programming in C/C++.

 

Program

1. Introduction to computing platforms (CPU, memory and peripherals).


2. AArch64 architecture. Cross-language calling conventions (invocation, parameter passing).


3. SIMD instructions for explicit data parallelism.


4. Single-cycle and multi-cycle CPU implementations.


5. Instruction level parallelism: “pipelining”; limitations; management of data and control dependencies.


6. Basics of CPU performance evaluation.


7. Common cache memory organizations and their impact on performance.


8. Basic organization of a “multi-core” processor; cache coherence and synchronization.


9. Interfacing with peripherals: polling, interrupts, DMA.


10. Data storage subsystem (magnetic disks, solid state drives, RAID).


11. Performance estimation of tasks that involve significant I/O activity.


12. Instruction-level parallelism: issuing multiple instructions; out of order execution.

Mandatory literature

David Patterson, John Hennessy; Computer Organization and Design: The Hardware/Software Interface ARM Edition, Elsevier / Morgan Kaufmann, 2016. ISBN: 9780128017333 (Note that other versions do not use the same CPU.)
Bruce Jacob; Spencer W. Ng ; David T.Wang; Memory Systems - Cache, DRAM, Disk (May be accessed through the Knovel Portal)
Jain, A., & Lee, C; Cache Replacement Policies, Morgan & Claypool , 2019. ISBN: 9781681735764

Teaching methods and learning activities

The curricular unit has a theoretical component based on lectures about the different themes accompanied by the presentation of examples and respective discussion. Theoretical-practical sessions include the presentation, analysis and resolution of a set of questions and case studies, as well as the discussion and resolution of problems that will be tested on a computational platform or on a CPU emulator.

Software

DS-5 Community Edition

keywords

Technological sciences > Engineering > Computer engineering

Evaluation Type

Distributed evaluation with final exam

Assessment Components

Designation	Weight (%)
Teste	100,00
Total:	100,00

Amount of time allocated to each course unit

Designation	Time (hours)
Estudo autónomo	110,00
Frequência das aulas	52,00
Total:	162,00

Eligibility for exams

Obtaining frequency requires that the limit of 3 absences from TP sessions is not exceeded.

Calculation formula of final grade

Distributed assessment consists of two tests (1h30 each).

The final grade (NF) is given by:

NF = T1 x 0.5 + T2 x 0.5 (final value rounded to units)

where T1 and T2 are the 1st and 2nd test scores, respectively (scale 0-20).

The re-take can be global (2H00 test) or partial (T1 or T2, 1H30 each).

Classification improvement

The course grade can be improved by taking a written test on the whole subject (2h00).

For students who take the tests in this academic semester, it is possible to improve the classification through a partial test (corresponding to the 1st or 2nd test) of 1H30.