A Binary Translation Framework for Automated Hardware Generation

• Tipo: Artigo em Revista Científica Internacional
• Data: 2021

Autores

Nuno Paulino (Autor) FEUP; João Bispo (Autor) FEUP; João Canas Ferreira (Autor) FEUP; João M. P. Cardoso (Autor) FEUP

Revista

Título: IEEE Micro

Vol. 41

Páginas: 15-22

ISSN: 0272-1732

Editora: IEEE

Indexação

ISI Web of Knowledge - 2 Citações

Scopus - 2 Citações

Outras Informações

ID Authenticus: P-00V-2EW

DOI: 10.1109/mm.2021.3088670

Abstract (EN): As applications move to the edge, efficiency in computing power and power/energy consumption is required. Heterogeneous computing promises to meet these requirements through application-specific hardware accelerators. Runtime adaptivity might be of paramount importance to realize the potential of hardware specialization, but further study is required on workload retargeting and offloading to reconfigurable hardware. This article presents our framework for the exploration of both offloading and hardware generation techniques. The framework is currently able to process instruction sequences from MicroBlaze, ARMv8, and riscv32imaf binaries, and to represent them as Control and Dataflow Graphs for transformation to implementations of hardware modules. We illustrate the framework's capabilities for identifying binary sequences for hardware translation with a set of 13 benchmarks.

Idioma: Inglês

Tipo (Avaliação Docente): Científica

Nº de páginas: 8