Hardware Support to Minimize the End-to-End Delay in Ethernet-Based Ring Networks

• Tipo: Artigo em Revista Científica Internacional
• Data: 2019

Autores

Correa, TP (Autor) Outra; Luis Almeida (Autor) FEUP

Revista

Título: Electronics (Switzerland)

Vol. 8

Página Final: 1097

ISSN: 2079-9292

Editora: MDPI

Indexação

ISI Web of Knowledge - 0 Citações

Scopus - 0 Citações

Outras Informações

ID Authenticus: P-00R-3ZC

DOI: 10.3390/electronics8101097

Abstract (EN): Ethernet is a popular networking technology in factory automation and industrial embedded systems, frequently using a ring topology for improved fault-tolerance. As many applications demand ever shorter cycle times and a higher number of nodes, the popular ring endure to remain as a valid topology. In this work, we discuss the factors that determine the ring network delay and show how they affect the network cycle time. Since increasing the link capacity has limited reach, we explore a time-triggered protocol that brings the nodes forwarding delay near to the physical layer delay. Additionally, we propose hardware accelerators based on FPGA technology that minimise the packet reception delay from physical reception to delivery to an application handler, preserving Ethernet layers and being compatible with its standard. This paper explains the accelerators concept and implementation, presents measurements using standard Media Access Control implementations, and shows the solution effectiveness with experimental results. We achieved a delay, from physical reception to the triggering of a user-level handler, of 1.1 mu s independent of the packet length.

Idioma: Inglês

Tipo (Avaliação Docente): Científica

Nº de páginas: 15